GB2461648A - Progammable two table indexed finite state machine - Google Patents

Abstract

A system stores an input compare vector in an input compare vector table. The system also stores an output vector, a next state value and a next state start address in an output vector, next state, next state address table. Each comparator compares each input compare vector from the input compare vector table and an external input vector, and outputs a selection signal to a multiplexer. The multiplexer associates the selection signals with an offset value, and provides the offset value to adder logic. The adder logic adds the offset value and an address from a current state start address register. A result of the addition is used as an address to access a row in the output vector, next state, next state address table. The accessed row has an output vector, a next state value and a next state start address corresponding to a current state and the external input vector.

Description

PROGRAMMABLE TWO TABLE INDEXED FINITE STATE MACHINE

Background

The present invention relates generally to Finite State Machines and more specifically to programmable Finite State Machines having more than one table.

Referring to Figs. 1 and 2, a prior art programmable Finite State Machine (FSM) 20 consists of a Transition Rule Memory (TRM; a memory storing a description or table describing state 1 0 transitions of a FSM) 26 comprising a single large table having all the transition rules that define the FSM. A programmable FSM refers to a FSM that can make state transitions based on a state transition table. Upon changing the transition table, state transitions of the FSM also becomes changed.

In Fig. 1, state transition rules Ri.. .R4 are stored in each row of the TRM and these rules are presented in parallel to Rule Selector logic 24. Rule Selector logic compares a test part 28 of each rule (see Figure 2) with a value of a current state (CS) register 25 and an external Input Vector. When the Rule Selector logic 24 finds a matching rule, an output vector in the result part 29 of that rule is sent as an output of the FSM. Also, a next state value of the matching rule is loaded into the current state register 25.

An address generator 27 generates an address for enabling access to the TRM 26 from the value of the CS register 25 and the Input Vector using a hashing scheme. The bits that are selected from the CS register 25 and the bits that are selected from the input vector are defined by a hash mask 22. For example, a hash mask bit of 1 defines that a corresponding input bit is selected as an address bit, and a hash mask bit of 0 defines that a corresponding current state bit is selected as an address bit. This hash mask 22 can be identical for all the states of the FSM or it can depend on a current state of the FSM. In the latter case, the hash mask 22 needs to be a part of an output of the rule selector logic 24 as shown in Figure 1. In the former case, the hash mask 22 is statically defined and is set up at initialization time.

Typical programmable finite state machines can be implemented using a table describing state transitions. However, most space in the table is unused and thus wasted as it can not be used for other purposes. Furthermore, traditional programmable finite state machines are not very efficient in handling Don't care values or Don't care bits in input vectors. Thus, a programmable finite state machine that can overcome these shortcomings would be desirable.

Referring to Fig. 3, there is shown an example of a traditional state transition table 37. A state transition table refers to a table describing all possible transitions of a FSM. The table 37 has 4 columns, a current state column, an input vector column, an output vector column, and a next state column. Values in the columns are symbolic values that represent state values (e.g., S2) or input/output vectors (e.g., ilO or olO). The table 37 is interpreted as follows: if a FSM operating based on the table 37 is currently in state S2 and the FSM receives an input 1 0 vector i2_2, the FSM will produce an output vector of o2_2 and make a transition to state S3 as described in a row 39 in the table 37. It is to be noted that transitions associated with a certain state are organized in adjacent rows. For example, transitions of state Si are described in the top two rows in the table 37, state transitions of state S2 are described in rows 3 to 6 in the table 37, and the transitions for state S3 are described in rows 7 and 8 in the table 37.

BRIEF SUMMARY

The present invention comprises a programmable finite state machine and methodology, the FSM having two small tables of data instead of a single large table. One of the two tables is completely used to store only possible state transitions; and the other table includes all the possible input vectors which influence a state on each line or row. This second table may not be completely used, but wasting of space is reduced compared to a prior art, which uses only a single large table.

Thus, in accordance with one embodiment of the present invention, there is provided a system of controlling a programmable Finite State Machine, the system comprising: means for storing an input compare vector in a first table, said input compare vector indicating a possible input vector of a state; means for storing an output vector, a next state value and a next state start address in a second table, the next state start address pointing to a first address of a set of transitions which are devoted to a state in a state transition table; at least one comparator receiving said input compare vector from the first table and an external input vector as inputs, and outputting one as a selection signal when said input compare vector and said external input vector matches; a first multiplexer coupled to said at least one comparator for receiving said selection signal from said at least comparator and associating the selection signal with an offset value; adder means coupled to said first multiplexer for receiving said offset value from said first multiplexer and a current state start address from a first register and generating a second address having a value equal to a sum of said received offset value and said received next state start address; and means for accessing a row in said second table based on said second address to obtain an output vector and a next state value in said row.

The foregoing has outlined, rather broadly, the preferred feature of the present invention so that those skilled in the art may befter understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claim of the invention. Those skilled in the art should appreciate that they can readily use the conception and specific embodiment as a base for designing or modifying the structures for carrying out the same purposes of the present invention and that such other features do not depart from the spirit and scope of the invention in its broadest form.

BRIEF DESCRJPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Other aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which similar elements are given similar reference numerals.

Fig. 1 illustrates a block diagram of a prior art programmable single table indexed finite state machine.

Fig. 2 illustrates a state transition rule format for the prior art programmable single table indexed finite state machine of Fig. 1.

Fig. 3 illustrates an exemplary state transition table of a prior art finite state machine.

Fig. 4 illustrates splitting the table from Fig. 3 into two tables according to one embodiment of the present invention.

Fig. 5 illustrates a block diagram of a programmable two table indexed finite state machine in accordance with one embodiment of the present invention.

Fig. 6 illustrates a block diagram of the programmable two table indexed finite state machine for handling "Don't cares" according to one embodiment of the present invention.

Figs. 7a and 7c illustrate how "otherwise" transitions are supported according to one embodiment of the present invention.

Fig. 8a illustrates another Input Compare Vector Table (ICVT) supporting a Programmable Two Table Indexed Finite State Machine (PTT FSM) as shown in Fig. 8b.

Fig. 8b illustrates a block diagram of the programmable two table indexed finite state machine according to one embodiment of the present invention; Fig. 8c illustrates an exemplary ICVT according to one embodiment of the present invention; Fig. 9 illustrates a block diagram of a programmable two table indexed finite state machine according to one embodiment of the present invention.

1 0 Fig. 10 illustrates an exemplary hardware configuration in accordance with one embodiment of the present invention.

DETATLED DESCRIPTION

Referring to Fig. 4, according to one embodiment of the present invention, a state transition 1 5 table 37 (i.e., a table describing state transitions of a FSM) in Fig. 3 is broken into two tables 42 and 52. The first table is an Input Compare Vector Table (ICVT) 42 that includes as many entries as there are states. The ICVT 42 is indexed by a Current State register (e.g., a CS register 46 in Fig. 5). The CS register stores a current state value of the FSM. The rows of table 42 are partitioned into columns where each column stores an input compare vector. The input vectors associated with one state are located in a single row of the ICVT 42. An input compare vector refers to a possible input vector that the FSM can receive as an input. The other table 52 is designated ONNT for Output vector, Next state, Next state address Table.

The ONNT 52 has the same number of rows as the state transition table 37, which is designated as OT-NS (Output Table Next State) table 37. The ONINT 52 includes an output vector, a next state value and a Next State Start Address (NSSA). The NSSA (Next State Start Address) points to the first address of a set of transitions which are devoted to a certain state.

For example, a row 80 of the ONNT 52 includes a value of 2 (112) as an NSSA and a next state value S2 (110). The first transition for state S2 is at the 2'" row (10) of the OTNS table 37. Therefore, the Next State Start Address for state S2 (110) is 2.

Fig. S illustrates a block diagram for a programmable finite state machine (i.e., a finite state machine whose state transitions can be changed upon changing a state transition table) utilizing the two tables (e.g., ICVT 42 and ONNT 52) according to one embodiment of the present invention. For ease of a description, it is assumed that a finite state machine operating based on the TCVT 42 and ONNT 52 is currently in state S2 and a CSSA register (Current State Start Address register which stores an NSSA) 40 has a value of 2 because a first state transition for state S2 is described in the 2' row (10) of the OTNS table 37. Upon starting a state transition execution, a computing system (e.g., a computing system 200 in Fig. 10) accesses the 1st row 114 of the ICVT 42 addressed by a CS (Current State) register 46. The CS register 46 may store S2 as a current state value and a state transition of S2 is described at the 1st row 114 of the ICVT table. The computing system 200 accesses the 1st row 114 of the ICVT 42, e.g., by calculating an accessing address, e.g., by executing a current state value-i.

Then, the computing system 200 retrieves four possible input vectors i20 to i2_3 of the 1 0 current state S2 from the 1st row 71 of the TCVT 1.

Then, the computing system 200 provides the retrieved four possible input vectors to a set of comparators C0-C3 44 as a first input of the comparators. The number of comparators may be equal to the number of columns in the ICVT 42. The computing system 200 also receives an external input vector 79 from a component other than a FSM and then provides the external input vector 79 as a second input of the comparators.

It is further assumed that the external input vector 79 includes a value that matches with an input comparator vector i21. Then, based on this assumption, a comparator Ci would have a match condition and set a corresponding selection signal C 1_Sd 116 to 1. All other comparators will not have a match condition and corresponding selection signals Cx Sd will be zero. The computing system 200 provides these selection signals as inputs to a multiplexer 50. The multiplexer 50 associates each selection signal with an offset value. For example, an offset value 0 is associated with Comparator 0, an offset value 1 is associated with comparator Ci and so on. In this example, the multiplexer 50 generates an offset value of 1, because the selection signal Ci_Sel is only 1. Then, the multiplexer 50 feds the generated offset value of 1 to an adder logic 48. The adder logic 48 also receives a value of 2 (i.e., a state start address of a current state S2) from the CSSA register 40 as another input. The CSSA register 40 stores a current state start address associated with the OTNS table 37. A result of the adder 48 will, therefore, have a value of 2+1=3. The computing system 200 uses the value of 3 as an address accessing the ONNT table 52, e.g., by pointing to a 3'' row (120) of the ONNT table 52. The row (120) stores state transition information associated with a current state S2 and an input vector i2i. Then, the computing system 200 provides an output vector o21 (122) in the row (120) to an output port of the FSM. The computing system 200 loads a next state value S3 in the row (120) into the CS register 46. The computing system 200 also loads a next state start address 6 (124) into the CSSA register 40 during a next clock cycle.

Referring now to Fig. 6, there is illustrated AND gates 62 that are added to the FSM in Fig. 5 in order to handle input vectors with a "Don't care" bit. The "Don't care" bit refers to a bit that can be either 0 or 1. In other words, the "Don't care" bit refers to undetermined or unknown bit. According to one embodiment of the present invention, each row of the ICVT 42 accessed by a current state value stored in the CS register 46 stores an input compare vector (e.g., an input compare vector iclO (128)) and an input mask field (e.g., imlO (130) 1 0 or imll(132)). The input mask field has the same bit width as the input compare vector.

A computing system (e.g., a computing system 200 in Fig. 10) receives an input vector having a "Don't care" bit. The computing system 200 stores a corresponding input mask field in the ICVT 42. The corresponding input mask field may have 0 at a corresponding position of the "Don't care" bit of the input vector and 1 at other corresponding positions. AND gates 62 performs a logical AND operation of the input vector having the "Don't care" bit and the corresponding input mask field, and generates an output of the logical AND operation. The computing system 200 stores the output of the logical AND operation as a corresponding input compare vector (e.g., iclO or icli) in the ICVT 42. For example, if an input vector i21 is 10x02, where the x represents a "Don't care" bit, which is either a 0 or a 1. In this example, the mask field for that input vector will be 1101, and the Input compare vector will be 1000, which is an output of (lOxO AND 1101). Thus, the AND gate 62 now ensure that an unknown value of the "Don't care" bit is forced to zero at the output of AND gate 62.

When the computing system 200 receives an external input vector 79, each AND gate 62 performs a logical AND operation of the external input vector 79 and each input mask field, and generates an output of the logical AND operation. Then, each AND gate 62 provides the output to a corresponding comparator 44, which compares the output of the logical AND operation and a corresponding input compare vector. Then, each comparator 44 generates a selection signal and provides the selection signal to the multiplexer 50 as illustrated in Fig. 5.

The computing system 200 operates the multiplexer 50 and the adder logic 48 as illustrated in Fig. 5 and accesses the ONNT 52.

In Figs. 7a-7c, a concept of OTHERWISE statement is introduced in a state transition table (e.g., an OTNS table 37). An OTHERWTSE statement refers to a statement to be executed if no WHEN condition is met (i.e., there is no corresponding specific pair of an input vector and a current state value in a state transition table (e.g., the OTNS table 37)). Fig. 7a illustrates an exemplary OTNS 78 using OTHERWISE statements. Referring to Fig. 7a, if in state 51 an input vector is neither ilO (row 134) nor il_i (row 136), then a state transition in a row 138 of the table 78 should be used, which causes a FSM using the table 78 to generate an output vector of ol_2 and make a transition to a state S3 during a next clock cycle. The table 78 shown in Fig. 7a is rewritten in Fig. 7b by moving all the state transitions containing an 1 0 Otherwise statement at the end of the OTNS table. The first row containing an Otherwise state transition is pointed to by the Sta_Addr_Other Reg (82 in Figs. 7b and 7c). In Fig. 7c, a value of the CS register 46 is used as an offset which is added to a value of the StaAddr_Other_Reg 82 to obtain the Otherwise state transition for the current state. In the exemplary FSM illustrated in Fig. 7c, it is assumed that the State Si is encoded as a decimal 1 5 0, the state S2 as a decimal 1 and so on.

Fig. 7c illustrates adding three elements to support a handling of OTHERWISE statements.

First, there is provided a NOR gate 81 or a similar NOR logic circuit for receiving selection signals Cx_Sel, which are outputs of a set of comparators 44. The set of comparators 44 detects whether there is a match between an external input vector 79 and a possible input vector from ICVT 42. If there is no match (i.e., all the Cx Sd signals from the comparators 44 are zero), an output indicated as Other_found of the NOR gate 81 becomes 1. The second element is the Sta_Addr Other register 82 which provides an address in the OTNS 78 for an OTHERWISE statement to a first multiplexer 50. In the exemplary FSM illustrated in Fig. 7b, the value contained in the Sta Addr Other register 82 would be 8. The third element is a second multiplexer 83 which selects either a current state start address (i.e., an address pointing to a first address of a set of transitions which are devoted to the current state in a state transition table) from the CSSA register 40 or a current state value from the CS register 46 as an input to adder logic 48. For example, if the Finite State Machine is in state S2 and there is no matching input vector found, then the Other_found signal would be 1 as described above. Therefore, Mux 50 will select the Sta Addr Other_Reg which contains a value of 8 and this value will be fed to an input of the adder 48. A multiplexer 83 will select the value of the CS register 46 which is 1 for state S2. The Adder circuit 48 will therefore generate an address of 9 which is the last entry of the ONNT containing the Otherwise statement for state S2.

If a programmable FSM shown in Fig.7c has implemented four comparators 44, then the number of possible state transitions for a specific state is limited to 4. Assuming that an additional state transition would be needed for S2, which already has 4 transitions, a structure illustrated in Fig. 7C could not support the additional state transition even if there would be free rows in the ICVT 42 that are available.

1 0 A solution to this problem is shown in Figs. 8a, 8b and 8c. In Fig. 8a, the ICVT table 42 is augmented with a new column 138, which stores an MSB (Most Significant Bit) value of an offset value received from a multiplexer 50.

Fig. 8b illustrates how the MSB value is used according to one embodiment of the present invention. An offset value 97 fed to an Adder logic 48 now is composed of an Offset M value 94 driven out of the ICVT 42 and an Offset L value driven by Mux_Offset 50. Concatenation logic 96 generates the offset value 97 based on Offset M and Offset L values, e.g., by concatenating the Offset M and the Offset_L. For example, the Offset M value becomes the MSB of the offset value 97. The Offset L becomes other bits of the offset value 97. Thus, the offset value 97 generated by the Concatenation logic 96 has an additional bit (i.e., 1 bit more than an offset value generated by the multiplexer 50 in Fig. 5), which is used to reach an additional row describing a new state transition in the ONNT 52. For example, the offset value 97 is fed to the adder logic 48, where the offset value 97 is added with a current state start address stored in CSSA register 40. An output (i.e. addition of the offset value 97 and the address from the CSSA register 40) of the adder logic 48 can be used as an address to access a new row (not shown) in the ONNT 51. An address generator logic 92 operates like the address generator 27 in Fig. 1 and generates an address accessing the ICVT 42 based on a value of the CS register 46 and the external input vector 79.

Fig. 8c is an example OTNS 140 of a FSM with 5 transitions defined for state S2 and a corresponding layout of the ICVT 42. In this example, the Offset M in the ICVT 42 will be a single bit. Note that the OTNS 140 in Fig. 8c include 5 rows for a current state value S2.

Fig. 9 illustrates a block diagram of a programmable finite state machine according to one embodiment of the invention. An address generator 92 generates an address accessing a row of the ICVT 42 based on a current state value stored in the CS register 46 and an external input vector 79. The accessed row in the TCVT 42 include, but is not limited to, all possible input vectors of a state and offset values provided to the multiplexer 50. Upon accessing a row in ICVT 42, a computing system (e.g., a computing system 200 in Fig. 10) provides input compare vectors (i.e., all possible input vectors of a state) in the row to comparators 44. There may be the same number of comparators to the number of input compare vectors. The comparators 44 also receive the external input vector 79 as another input. Each comparator 1 0 compares the external input vector 79 and an input compare vector provided from the ICVT 42, and generates an output which is fed to each AND gate 102. For example, if a comparator finds a match between the external input vector 79 and an input compare vector provided from the ICVT 42, that comparator generates 1 as an output. Otherwise, that comparator generates 0. There may be the same number of AND gates 102 as the number of comparators 44. An AND gate 102 receives the output from a corresponding comparator 44 and a comparator enable signal provided from a comparator enablement logic 100. The enable signal represents whether an output of a corresponding comparator is forwarded to the multiplexer 50 or not. The comparator enablement logic 100 may be a register storing binary numbers. For example, when the enable signal is 1111 (i.e., the logic 100 has a value of 1111), the AND gates 102 forwards all the comparator outputs to the multiplexer 50 as selection signals. When the enable signal is 1100, AND gates 102 corresponding C3 and C2 comparators forwards outputs from the C3 and C2 comparators to the multiplexer 50 (i.e., outputs from C3 and C2 comparators becomes outputs of the AND gates 102), and other AND gates 102 generates 0, which is fed to the multiplexer 50. Thus, the AND gates 102 generates selection signals, which composed of outputs of the AND gates and Os. The multiplexer 50 associates the selection signals from the AND gates 102 with offset values from the accessed row in the ICVT 42. For example, if C3 comparator generates 1 and the enable signal is 1, then a corresponding selection signal becomes 1 and a corresponding offset value (e.g., f3_O or f30) is fed to adder logic 48. The adder logic 48 adds a current state start address from the CSSA register 40 and the offset value associated by the multiplexer 50. The output of the adder logic 48 becomes an address for accessing a row of the ONNT 52. Upon accessing a row in the ONNT 52 using the address provided from the adder logic 48, the computing device 200 stores a next state value in that row into the CS register 46, The computing device 200 stores a (comparator) enable signal in that row into the comparator enablement logic 100. The computing device 200 provides an output vector in the row as an output. The computing device 200 stores a NSSA in that row in the CSSA register 40.

In the invention, two tables (e.g., ICVT 42 and ONNT 52) are used to store state transition information describing a FSM. The two tables are smaller than a traditional state transition table. The first table, the Input Compare Vector Table (ICVT) 42 stores only the input compare vectors. The ICVT 42 is accessed using a value stored in the CS Register 46. The second table, the ONNT 52, stores output vectors, next state values and Next State Start Addresses (NSSAs). An NSSA is copied into the CSSA register 40 in the same way as the 1 0 next state value is copied into the CS register 46.

Thus, according to one embodiment of the present invention, a finite state machine has two tables. One table is IICVT 42 and the other table is an ONNT 52. The IICVT 42 stores a set of input vectors that corresponds to a current state. All of the input vectors stored in the ICVT 42 are compared with an external input vector. The ONNT 52 stores an output vector, a next state value and a next state start address. From the ICVT, an offset value is calculated, e.g., by using a multiplexer 50. That offset value is added to an address in the CSSA register 40.

Then, a result of the addition is used as an address to access a row in the ONNT 52.

A computer-based system is depicted in Fig. 10 herein by which the method of the present invention may be carried out. Computer system includes a processing unit, which houses a processor, memory and other systems components that implement a general purpose processing system or computer that may execute a computer program product. The computer program product may comprise media, for example a compact storage medium such as a compact disc, which may be read by the processing unit through a disc drive, or by any means known to the skilled artisan for providing the computer program product to the general purpose processing system for execution thereby.

The computer program product comprises all the respective features enabling the implementation of the methods described herein, and which -when loaded in a computer system -is able to carry out these methods. Computer program, software program, program, or software, in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: (a) conversion to another language, code or notation; and/or (b) reproduction in a different material form.

The computer program product may be stored on hard disk drives within processing unit (as mentioned) or may be located on a remote system such as a server (not shown), coupled to processing unit, via a network interface such as an Ethernet interface. Monitor, mouse and keyboard are coupled to the processing unit, to provide user interaction. Printer is shown coupled to the processing unit via a network connection, but may be coupled directly to the processing unit.

More specifically, as shown in Fig. 10, the computer system 200, includes one or more processors or processing units 210, a system memory 250, and an address/data bus structure 201 that connects various system components together. For instance, the bus 201 connects the processor 210 to the system memory 250. The bus 201 can be implemented using any kind of bus structure or combination of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures such as ISA bus, an Enhanced ISA (EISA) bus, and a Peripheral Component Interconnects (PCI) bus or like bus device. Additionally, the computer system 200 includes one or more monitors 219 and, operator input devices such as a keyboard, and a pointing device (e.g., a "mouse") for entering commands and information into computer, data storage devices, and implements an operating system such as Linux, various Unix, Macintosh, MS Windows OS, or others.

The computing system 200 additionally includes: computer readable media, including a variety of types of volatile and non-volatile media, each of which can be removable or non-removable. For example, system memory 250 includes computer readable media in the form of volatile memory, such as random access memory (RAM), and non-volatile memory, such as read only memory (ROM). The ROM may include an input/output system (BIOS) that contains the basic routines that help to transfer information between elements within computer device 200, such as during start-up. The RAM component typically contains data and/or program modules in a form that can be quickly accessed by processing unit. Other kinds of computer storage media include a hard disk drive (not shown) for reading from and writing to a non-removable, non-volatile magnetic media, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from and/or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM, or other optical media. Any hard disk drive, magnetic disk drive, and optical disk drive would be connected to the system bus 201 by one or more data media interfaces (not shown).

Alternatively, the hard disk drive, magnetic disk drive, and optical disk drive can be connected to the system bus 201 by a SCSI interface (not shown), or other coupling mechanism. Although not shown, the computer 200 can include other types of computer readable media. Generally, the above-identified computer readable media provide non- 1 0 volatile storage of computer readable instructions, data structures, program modules, and other data for use by computer 200. For instance, the readable media can store an operating system (O/S), one or more application programs, such as video editing client software applications, and/or other program modules and program data for enabling video editing operations via Graphical User Interface (GUI). Input/output interfaces 245 are provided that couple the input devices to the processing unit 210. More generally, input devices can be coupled to the computer 200 through any kind of interface and bus structures, such as a parallel port, serial port, universal serial bus (USB) port, etc. The computer environment 200 also includes the display device 219 and a video adapter card 235 that couples the display device 219 to the bus 201. In addition to the display device 219, the computer environment 200 can include other output peripheral devices, such as speakers (not shown), a printer, etc. I/O interfaces 245 are used to couple these other output devices to the computer 200.

As mentioned, computer system 200 is adapted to operate in a networked environment using logical connections to one or more computers, such as A server device that may include all of the features discussed above with respect to computer device 200, or some subset thereof. Tt is understood that any type of network can be used to couple the computer system 200 with the server device, such as a local area network (LAN), or a wide area network (WAN) (such as the Internet). When implemented in a LAN networking environment, the computer 200 connects to local network via a network interface or adapter 229. When implemented in a WAN networking environment, the computer 200 connects to the WAN via a high speed cable/dsl modem 280 or some other connection means. The cable/dsl modem 280 can be located internal or external to computer 200, and can be connected to the bus 201 via the I/O interfaces 245 or other appropriate coupling mechanism. Although not illustrated, the computing environment can provide wireless communication functionality for connecting computer 200 with remote computing device, e.g., an application server (e.g., via modulated radio signals, modulated infrared signals, etc.).

Although a few examples of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes might be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.

Claims (6)

1. CLAIMS1. A system of controlling a programmable Finite State Machine, the system comprising: means for storing an input compare vector in a first table, said input compare vector indicating a possible input vector of a state; means for storing an output vector, a next state value and a next state start address in a second table, the next state start address pointing to a first address of a set of transitions which are devoted to a state in a state transition table; 1 0 at least one comparator receiving said input compare vector from the first table and an external input vector as inputs, and outputting one as a selection signal when said input compare vector and said external input vector matches; a first multiplexer coupled to said at least one comparator for receiving said selection signal from said at least comparator and associating the selection signal with an offset value; 1 5 adder means coupled to said first multiplexer for receiving said offset value from said first multiplexer and a current state start address from a first register and generating a second address having a value equal to a sum of said received offset value and said received next state start address; and means for accessing a row in said second table based on said second address to obtain an output vector and a next state value in said row.
2. 2. The system of claim 1 further comprising: means for receiving an input vector having a Don't care bit; and means for storing a mask field having a bit width equal to the input vector having the Don't care value, having 0 at a corresponding position of the Don't care bit of the input vector and having 1 at other corresponding positions; at least one AND gate performing an logical AND operation of the input vector having the Don't care bit and the mask field and generating an output of the logical AND operation; and means for storing the output of the logical AND operation as said input compare vector in said first table.
3. 3. The system of claim 2 further comprising: said at least one AND gate performing said logical AND operation of said external input vector having a Don't care value and a mask field, and generating an output of said logical AND operation.
4. 4. The system of claim 1, further comprising: a NOR gate receiving selection signals from said at least one comparator as inputs and performing a logical NOR operation of the received selection signals; a register device coupled to said first multiplexer for providing a start address for an 1 0 OTHERWISE statement, said OTHERWISE statement being executed when there is no corresponding specific pair of an input vector and a current state value in said state transitiontable; anda second multiplexer coupled to said NOR gate for selecting either a value from a second register storing a current state value or an address from said first register and 1 5 providing a selected value or address to said adder means.
5. 5. The system of claim 1, further comprising: means for storing a MSB (Most Significant Bit) of said offset value in said first table; means for concatenating other bits of said offset value and said MSB of said offset value to generate said offset value, said other bits of said offset value provided from said first multiplexer, whereby a number of bits in said offset value is extended to reach an additional row describing a new state transition in said second table.
6. 6. The system of claim 1, further comprising: means for storing said offset value in said first table; said first multiplexer selecting said offset value provided from the first table by associating with said selection signal; and a register device storing a binary number indicating a comparator enable signal, said comparator enable signal representing whether an output of a corresponding comparator is forwarded to said first multiplexer or not.