WO2023166609A1

WO2023166609A1 - Device for assisting with digital circuit design, method for assisting with digital circuit design, and program for assisting with digital circuit design

Info

Publication number: WO2023166609A1
Application number: PCT/JP2022/008868
Authority: WO
Inventors: 哲人深井; 悠太石山
Original assignee: 三菱電機株式会社
Priority date: 2022-03-02
Filing date: 2022-03-02
Publication date: 2023-09-07
Also published as: JPWO2023166609A1

Abstract

Provided is a device (100) for assisting with digital circuit design. The device (100) comprises: a memory map generation unit that generates a memory map; and a hardware description generation unit that generates a hardware description. The hardware description generation unit generates a description of a port to be used by an external circuit (130) to communicate with a memory map circuit (120). The port description describes a circuit which is separate from a writing circuit and a reading circuit which go through a bus of a register included in the memory map.

Description

Apparatus for supporting digital circuit design, method for supporting digital circuit design, and program for supporting digital circuit design

The present disclosure relates to technology for supporting digital circuit design, and more specifically to technology for automatically generating various hardware descriptions.

　In the field of hardware design such as digital circuits, there is a concept of pairs of addresses and storage areas (registers) called memory maps or register maps. Each register included in the memory map may have attributes such as W (writable: write only), R (readable: read only), RW (readable), and various other functions. be.

In the hardware design process, a memory map is generally created first, and a hardware description is created based on the attributes and function definitions of each register defined in the memory map. Further, hardware is manufactured based on the hardware description. Depending on the hardware description language, there is a technique for automatically generating the hardware description based on the attribute information of each register defined in the memory map.

Conventional hardware description automatic generation technology only supports the generation of descriptions for the main attributes of registers, W (writable), R (readable), and RW (readable). Therefore, a circuit with a special function such as a circuit in which a register to be written and a register to be read are different, or a circuit in which a register is rewritten by access from a circuit different from the normal read circuit or write circuit. It was not possible to automatically generate a hardware description of As a result, in order to realize these special functions, it was necessary for the user to add and correct the description of the special functions in the automatically generated hardware description.

If the hardware description is manually modified, special functions can also be realized. An increase in the number of man-hours may occur due to the omission of reflecting the description and the task of reflecting the description of the special function. Therefore, there is a need for a technology that more efficiently supports hardware design.

Regarding the technology for supporting digital circuit design, for example, Japanese Patent Application Laid-Open No. 2005-309584 (Patent Document 1) describes, "Inside a digital circuit that is predefined by a hardware description language and consists of a combination of a register and a combinational circuit, A database in which templates containing undefined words indicating both or one of wiring and wiring between a digital circuit and the outside are registered in advance, internal wiring, and a digital circuit Storage means storing the design specifications of a digital circuit in which wiring to the outside is defined in advance as the transfer of information to a register, and a word indicating the transfer of information to the register defined as the design specifications in an undetermined word and specification reflection means for generating a string of statements representing the digital circuit in a hardware description language by substituting .

JP 2005-309584 A

According to the technology disclosed in Patent Document 1, it is not possible to automatically generate hardware descriptions for circuits with special functions other than read circuits or write circuits. Therefore, there is a need for techniques for automatically generating hardware descriptions for special function circuits other than read or write circuits.

The present disclosure has been made in view of the background as described above, and an object in one aspect is to provide a technique for automatically generating a hardware description for a circuit with special functions other than a read circuit or a write circuit. to provide.

According to one embodiment, an apparatus is provided for supporting digital circuit design. The apparatus comprises a memory map generator for generating a memory map and a hardware description generator for generating a hardware description based on the memory map. A hardware description generator generates descriptions of ports for external circuits to communicate with circuits in the memory map. A port description is a description of a circuit separate from the write and read circuits via a bus of registers contained in the memory map.

According to an embodiment, it is possible to automatically generate hardware descriptions for special function circuits other than read or write circuits.

The above and other objects, features, aspects and advantages of this disclosure will become apparent from the following detailed description of the disclosure taken in conjunction with the accompanying drawings.

1 is a diagram showing an example of an overview of functions of an apparatus 100 for hardware design support according to an embodiment; FIG. 2 is a diagram illustrating an example of a hardware configuration of device 100; FIG. 3 is a diagram showing an example of functional blocks of software 300. FIG. 3 is a diagram showing a first example of a UI (User Interface) 304; FIG. FIG. 11 is a diagram showing a second example of UI 304; FIG. 10 is a diagram showing an example of setting values that can be input to register setting items 530. FIG. FIG. 3 is a diagram showing an example of the description of the highest hierarchy in the hardware description; FIG. 3 is a diagram showing an example of description of bus protocol control in hardware description; FIG. 10 is a diagram showing an example of a hardware description of a register 121 with RW attributes; 9 is a schematic diagram showing an example of a circuit corresponding to the hardware description 900; FIG. FIG. 10 is a diagram showing an example of a hardware description of a W-attribute register 121. FIG. 11 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1100; FIG. FIG. 4 is a schematic diagram showing an example of an R-attribute circuit; FIG. 12 is a diagram showing a first example of hardware description of the register 121 when the value of the option setting item 533 is "sp"; 14 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1400; FIG. FIG. 13 is a diagram showing a second example of hardware description of the register 121 when the value of the option setting item 533 is "sp"; 16 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1600; FIG. FIG. 13 is a diagram showing an example of hardware description of the register 121 when the value of the option setting item 533 is “sn”; 18 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1800; FIG. FIG. 3 is a diagram showing an example of a hardware description generation procedure by the apparatus 100;

Hereinafter, embodiments of the technical idea according to the present disclosure will be described with reference to the drawings. In the following description, the same parts are given the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

<A. Overview of Functions of Devices Supporting Digital Circuit Design>
FIG. 1 is a diagram showing an example of an outline of functions of a device 100 for hardware design support according to the present embodiment. The device 100 executes the hardware design support software 300 to generate a hardware description including a description of special function circuits other than the read circuit or the write circuit.

In this specification, the term "device" refers to a configuration consisting of one or more devices, a server, a virtual machine or container built in a cloud environment, or a system composed of at least a part of these. contain. Also, the device may include an information processing device such as a personal computer, workstation, server device, tablet, smart phone, or a combination thereof. In one aspect, device 100 may be used by a user by being connected to input/output devices such as a display and keyboard. In other aspects, device 100 may provide various functions to the user as a cloud service or web application via a network. In this case, the user may use the functionality of device 100 via a browser or client software installed on his terminal.

In this specification, the term "hardware description" or "description" refers to a description of the entire circuit, a description of a part of the circuit or a function written in Hardware Description Language (HDL). , or a file containing these descriptions (hardware description file).

The device 100 (software 300) mainly provides three functions. The first function is to define a special function circuit other than the read circuit or write circuit for each register included in the memory map, and to define the presence or absence of the register. The second function is to define circuits with special functions other than read circuits or write circuits, and to generate a file representing a memory map containing information on the presence or absence of registers. The third function is to automatically generate a hardware description including circuits with special functions other than read circuits or write circuits and/or circuits that do not contain registers from a file representing a memory map. Here, unlike the read circuit or the write circuit, the "special function circuit" means a port (each port shown in FIGS. 9 to 19) that communicates with the register without going through the bus protocol control circuit and the bus. is.

First, the first function (function for defining a special function circuit other than the read circuit or write circuit for each register included in the memory map and for defining the presence or absence of the register) will be described.

A circuit 110 is a circuit to be designed by a user, and includes a circuit 120 and a user circuit 130 as main components. Circuit 120 is a circuit designed based on the memory map generated by device 100 . User circuit 130 is a user-defined circuit that may communicate with circuit 120 as desired.

Circuit 120 includes one or more registers 121 and a bus protocol control circuit 122 . In one aspect, register 121 may be a register that includes one or more flip-flop circuits. In this case, one register 121 can be treated as a "unit of register" indicating a set of functions. In other aspects, register 121 may represent a single flip-flop circuit. In this case, a group of a plurality of registers 121 can be treated as a "register unit" indicating a group of functions. A bus protocol control circuit 122 is a circuit that provides a communication function to the register 121 . If the register 121 has any of the attributes R attribute (readable), W attribute (writable), or RW attribute (readable), other circuits, via the bus protocol control circuit 122 and the bus, Reading data from register 121 and writing data to register 121 may be performed.

All processing of the R attribute and W attribute for the register 121 is executed via the bus protocol control circuit 122. However, depending on the functionality to be provided by circuit 110, user circuit 130 may need to communicate with register 121 without using the bus protocol (via bus protocol control circuit 122 and the bus). Therefore, the device 100 provides the user with means for setting special functions in addition to the R attribute, W attribute, and RW attribute for each register 121 included in the memory map. The user can set special functions for each of the registers 121 in addition to the R attribute, W attribute, and RW attribute via the UI 304 (see FIG. 3). As a result, the device 100 can generate the circuit 145, which could not be automatically generated by the conventional hardware description automatic generation technology, in addition to the R-attribute, W-attribute, and RW-attribute circuits (circuit 140). can. As an example, the device 100 may determine whether or not to generate a special function circuit by receiving a register 121 or a bitwise option contained in the register 121 .

Furthermore, the device 100 can generate a circuit that does not include the registers 121 by accepting options for each register 121 . A circuit that does not include the register 121 is a circuit that does not have a storage area (flip-flop circuit). However, a circuit that does not include the register 121 may include a bus protocol control circuit, a read circuit, a write circuit, and other special function circuits other than the storage area.

Next, the second function (function for defining circuits with special functions other than read circuits or write circuits and for generating files representing memory maps containing information on the presence or absence of registers) will be described.

The device 100 generates a file representing the memory map defined by the first function. The “file representing the memory map” here is, for example, an IP-XACT file (xml (Extensible Markup Language) file). An IP-XACT file is a file that conforms to the standards defined by the IEEE-1685 standard (IP-XACT). The device 100 generates an IP-XACT file representing a memory map that includes special features other than the R, W, RW attributes and/or does not contain some or all of the registers 121 . By doing so, the device 100 can improve the reusability of the description of the special function included in the memory map without depending on the hardware configuration.

Finally, a third function (a function for automatically generating a hardware description including a circuit with special functions other than a read circuit or a write circuit and/or a circuit that does not include registers from a file representing a memory map). will be explained.

The device 100 interprets a file representing a memory map containing descriptions of special functions and generates a hardware description. The hardware description includes descriptions such as special functions other than the R attribute, W attribute, and RW attribute, and/or whether the register 121 is included or not, which could not be automatically generated conventionally.

By providing the above three functions, the device 100 can automatically generate a description that indicates whether or not the special function and/or the register 121 is included, even if the user changes the description of the memory map. As a result, the device 100 can suppress the omission of reflecting the description of the special function to the document or circuit (hardware description), etc., and the increase in man-hours due to the reflecting work when the hardware is modified.

<B. Device Hardware and Software Configuration>
FIG. 2 is a diagram showing an example of the hardware configuration of the device 100. As shown in FIG. The hardware configuration of the device 100 will be described with reference to FIG. The device 100 includes a processor 201, a memory 202, a storage 203, an output IF (Interface) 204, an input IF 205, a communication IF 206, an external device IF 207, and an internal bus 208 as main components. In one aspect, device 100 may be implemented as a server, cluster, or cloud environment by combining the hardware shown in FIG.

The processor 201 can execute software 300 for implementing various functions of the device 100 . Processor 201 is configured by, for example, at least one integrated circuit. Integrated circuits include, for example, at least one CPU (Central Processing Unit), at least one GPU (Graphics Processing Unit), at least one FPGA (Field Programmable Gate Array), at least one ASIC (Application Specific Integrated Circuit), or these It may be configured by a combination.

The memory 202 stores software 300 executed by the processor 201 and data referenced by the processor 201 . In one aspect, the memory 202 may be realized by DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), or the like.

The storage 203 is a non-volatile memory and may store software 300 executed by the processor 201 and data referenced by the processor 201 . In that case, the processor 201 executes the software 300 read from the storage 203 to the memory 202 and refers to the data read from the storage 203 to the memory 202 . In one aspect, the storage 203 may be realized by a HDD (Hard Disk Drive), SSD (Solid State Drive), EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), flash memory, or the like. .

The output IF 204 can be connected to any output device such as a CRT display, a liquid crystal display, or an organic EL (Electro-Luminescence) display. In one aspect, the output IF 204 may be realized by a USB (Universal Serial Bus) terminal, a D-sub terminal, a DVI (Digital Visual Interface) terminal and an HDMI (registered trademark) (High-Definition Multimedia Interface) terminal.

The input IF 205 can be connected to any input device such as a keyboard, mouse, touchpad or gamepad. In one aspect, the input IF 205 may be realized by a USB terminal, a PS/2 terminal, a Bluetooth (registered trademark) module, and the like.

The communication IF 206 is connected to wired or wireless network equipment. In one aspect, the communication IF 206 may be implemented by a wired LAN (Local Area Network) port, a Wi-Fi (registered trademark) (Wireless Fidelity) module, or the like. In another aspect, the communication IF 206 may transmit and receive data using communication protocols such as TCP/IP (Transmission Control Protocol/Internet Protocol) and UDP (User Datagram Protocol).

The external device IF 207 can be connected to arbitrary external devices such as printers, scanners and external HDDs. In one aspect, the external device IF 207 may be realized by a USB terminal or the like.

The internal bus 208 directly or indirectly connects the processor 201, the memory 202, the storage 203, the output IF 204, the input IF 205, and part or all of the communication IF 206 and the external device IF 207 so that they can communicate with each other.

FIG. 3 is a diagram showing an example of functional blocks of the software 300. FIG. Functional blocks included in the software 300 will be described with reference to FIG. In one aspect, some or all of the functional blocks shown in FIG. 3 may be implemented as program modules, libraries, or services that can independently communicate with each other.

The software 300 includes a memory map generation unit 301, an IP-XACT generation unit 302, a hardware description generation unit 303, and a UI 304 as main components.

The memory map generation unit 301 generates a memory map from various settings input via the UI 304. The generated memory map may contain one or more registers 121 . An initial value, attributes (R attribute, W attribute, RW attribute), and options (presence/absence of special function, presence/absence of register 121 (storage area)) are set in each register 121 . Memory map generator 301 outputs the generated memory map to IP-XACT generator 302 .

The IP-XACT generation unit 302 (also called an intermediate file generation unit) converts the memory map output by the memory map generation unit 301 into an IP-XACT file (xml file). IP-XACT generator 302 outputs the generated IP-XACT file to hardware description generator 303 . The generated IP-XACT file contains information on the initial values of registers 121, attributes, and options. In one aspect, the IP-XACT generator 302 may generate a file of any format other than the IP-XACT(xml) file from the memory map. In this case, the device 100 generates the hardware description from a file in a format other than the generated IP-XACT(xml) file.

A hardware description generation unit 303 generates a hardware description from an IP-XACT file (xml file). The generated hardware description includes, in addition to the attributes (R attribute, W attribute, RW attribute) of each register 121, a description for realizing optionally specified functions. In one aspect, hardware description generator 303 may generate the hardware description directly from the memory map.

The UI 304 is configured to accept various settings of the memory map. If the software 300 is a web application, the device 100 delivers the UI 304 to the user's terminal. The terminal may use a browser or client software to display the UI 304 on the display. UI 304 also outputs the generated IP-XACT file and/or the hardware description. The UI 304 may determine whether to output both the generated IP-XACT file and the hardware description, or to output either one, based on the user's operation. UI 304 may also output the hardware description as one or more files (hardware description files).

<C. Example of UI 304>
Next, an example of UI 304 provided by device 100 (software 300) will be described with reference to FIGS. 4 to 6. FIG. Via the UI 304, the user can input options (presence/absence of special functions, presence/absence of register 121) in addition to initial values and attributes (R attribute, W attribute, and RW attribute).

FIG. 4 is a diagram showing a first example of the UI 304. FIG. Screen 400 is part of UI 304 . A screen 400 is a screen for setting the highest layer of the register map, bus protocol information, and the like. Screen 400 includes interface setting item 401 , module name setting item 402 , data width setting item 403 , register map setting item 404 , and port setting item 405 . Each setting item may be a selection type setting item or an input type setting item.

The interface setting item 401 is an item for setting bus protocol information for accessing the register 121 . Bus protocol information may include AXI4-Lite and Avalon, etc., as examples. Based on the bus protocol information set in the interface setting item 401, the hardware description generation unit 303 generates a description of signal groups necessary for the bus protocol.

The module name setting item 402 is an item for setting the highest module name of the register map.

A data width setting item 403 is an item for setting the data width of the register 121 .
A register map setting item 404 is an item for setting the initial value, attribute, and option of the register 121 . The register map setting item 404 may be able to receive settings for a plurality of registers 121 for each memory map, or may be able to receive settings for one register 121 for each memory map. In one aspect, software 300 may display screen 500 as a dialog or window on the display of device 100 based on selection of register map setting 404 . In another aspect, software 300 may cause screen 400 to transition to screen 500 based on selection of register map setting item 404 .

The port setting item 405 is the type of port connected to the user circuit 130 . The ports set in port setting item 405 can be used as special function circuits other than standard read and write circuits.

FIG. 5 is a diagram showing a second example of the UI 304. FIG. Screen 500 is part of UI 304 . A screen 500 is a setting screen for each register 121 . Device 100 may display

screens

400 and 500 simultaneously on the display. Further, the device 100 may switch between the screen 400 and the screen 500 and display them on the display based on the user's operation.

The screen 500 includes an address setting item 510, a register name setting item 520, and a register setting item 530. The address setting item 510 includes an absolute address setting item 511 and an offset address setting item 512 . The register setting items 530 also include attribute setting items 531 , initial value setting items 532 , and option setting items 533 .

The address setting item 510 is an item for setting the start address of the register 121 . The user can input an absolute address to the absolute address setting item 511 as the top address of the register 121 . Also, the user can input an offset address from the reference address to the offset address setting item 512 as the top address of the register 121 . Note that the user may enter the address of the register 121 in either one of the absolute address setting item 511 and the offset address setting item 512, or may enter the address of the register 121 in both.

A register name setting item 520 is an item for setting the name of the register 121 . The register name set in the register name setting item 520 is used for generating the IP-XACT file and hardware description. In some aspects, software 300 may generate the hardware description directly from the memory map.

The register setting item 530 is an item for setting various information of the register 121 . The attribute setting item 531 is an item for setting any of the R attribute, W attribute, and RW attribute in the register 121 . The initial value setting item 532 is an item for setting the initial value of the register 121 (the value input to the register 121 when the register 121 is reset). The initial value setting item 532 is configured so that an initial value can be set for each bit of the register 121 . The option setting item 533 is an item for setting whether or not to generate a special function circuit in the register 121, whether or not the memory map includes the register 121, and the like.

FIG. 6 is a diagram showing an example of setting values that can be input to the register setting items 530. FIG. The attribute setting item 531 is configured such that any one of “RW (readable)”, “R (readable)”, and “W (writable)” can be set. The initial value setting item 532 is configured so that each bit can be set to “0” or “1”. As an example, the option setting item 533 is configured so that "no option", "rc", "rs", "sp", and "sn" can be set. Note that the selection items of the option setting items 533 shown in FIG. 6 are only examples, and the selection items of the option setting items 533 are not limited to these. In one aspect, the option setting item 533 may be configured to be able to set arbitrary options other than the options illustrated in FIG. Also, the option type may be expressed by a combination of alphanumeric characters other than "no option", "rc", "rs", "sp", and "sn".

"sp" is an option for creating a circuit with ports as described in FIG. 15 or FIG. "sn" is an option for generating a circuit with an internal structure that excludes register 121 from the structure of "sp". A circuit having an internal structure excluding the register 121 is a circuit that does not have a storage area due to a flip-flop circuit, and may have a write circuit and a read circuit. "rs" is an option that generates the same circuit as "sp" and automatically generates an auxiliary code that clears the register value to 0 when reading in the upper layer. "rs" is an option that generates the same circuit as "sp" and automatically generates auxiliary code that sets the register value to 1 at the time of reading in the upper hierarchy.

<D. Example of Generated Hardware Description and Circuit>
Next, the hardware description generated by device 100 (software 300) and a circuit corresponding to the hardware description will be described with reference to FIGS. 7 to 19. FIG. The

hardware descriptions

700 and 800 shown in FIGS. 7 and 8 are generated mainly based on the setting contents of the screen 400 (attribute information and the like may include the setting contents of the screen 500). The hardware descriptions and circuits shown in FIGS. 9-19 are generated primarily based on the settings on screen 500. FIG.

FIG. 7 is a diagram showing an example of the description of the highest hierarchy in the hardware description. The hardware description generation unit 303 generates a hardware description 700 of the highest layer of the memory map as shown in FIG.

FIG. 8 is a diagram showing an example of description of bus protocol control in hardware description. The hardware description generation unit 303 generates a bus protocol control hardware description 800 as shown in FIG. A bus protocol control description is generated as a hardware description of a sub-hierarchy of the memory map.

The device 100 (software 300) further generates a hardware description of the register 121 as one of the hardware descriptions of the subhierarchies of the memory map. The hardware description of the register 121 includes the setting contents of attributes, initial values, and options of the register 121 . A hardware description of the register 121 and a circuit corresponding to the hardware description of the register 121 will be described below for each setting content of the register setting item 530 .

(a. Circuit example with RW attribute)
9 and 10, an example of a hardware description of register 121 and a circuit corresponding to the hardware description of register 121 when attribute setting item 531 has a value of "RW (readable)". explain. It is assumed that the value of the option setting item 533 is "no option".

FIG. 9 is a diagram showing an example of the hardware description of the RW attribute register 121. FIG. A hardware description 900 is an example of a hardware description that is automatically generated when the value of the attribute setting item 531 is "RW (readable)" and the value of the option setting item 533 is "no option". The hardware description 900 includes a normal hardware description (description of the register 121 with RW attribute) and a port 1006 for the user circuit 130 to read the current value of the register 121 without using the bus protocol control circuit 122 . (see FIG. 10).

Based on the memory map, the device 100 generates a description 910 related to a special function circuit (a port that outputs the current value of the register 121 to the user circuit 130) other than the normal RW attribute. The description 910 makes the current value of the register 121 available to the user circuit 130 without going through the bus protocol control circuit 122 . Moreover, even if a hardware design change occurs, the device 100 automatically generates the description 910 based on the settings input via the

screens

400 and 500 . Therefore, the apparatus 100 can prevent the omission of reflecting the description of the special function to the document or circuit (hardware description) when the hardware is modified.

FIG. 10 is a schematic diagram showing an example of a circuit corresponding to the hardware description 900. FIG. The circuit 1000 is the circuit of the RW attribute register 121 . More specifically, circuit 1000 consists of a flip-flop circuit 1005 that stores data in register 121 and its peripheral circuits. In addition, the circuit 1000 is part of the circuit 120 (memory map circuit) (circuit corresponding to one register 121).

The circuit 1000 includes a bus circuit 1001, a read circuit 1002, a write circuit 1003, a selector 1004, a flip-flop circuit 1005, and a port 1006 as main components. In the example of FIG. 9, only one flip-flop circuit 1005 is shown for simplification of the drawing, but the register 121 is a storage area (flip-flop circuit) corresponding to the data width set in the data width setting item 403. circuit 1005).

The bus circuit 1001 is a circuit for communicating with the protocol set in the interface setting item 401. The bus circuit 1001 is a part of the bus protocol control circuit 122 or the bus protocol control circuit 122 generated for each register 121 . External circuitry typically performs read and write operations to register 121 via bus circuit 1001 .

The read circuit 1002 is a circuit for processing (read access) to read the data stored in the register 121 (the value stored in the flip-flop circuit 1005). Read circuit 1002 outputs data stored in register 121 (flip-flop circuit 1005) to an external circuit via bus circuit 1001 (bus protocol control circuit 122).

The write circuit 1003 is a circuit for writing data (write access) to the register 121 (flip-flop circuit 1005). The write circuit 1003 writes data acquired from an external circuit to the register 121 (flip-flop circuit 1005) via the bus circuit 1001 (bus protocol control circuit 122).

A selector 1004 controls the timing of writing data to the flip-flop circuit 1005 . For example, the selector 1004 may write data to the flip-flop circuit 1005 at the timing of receiving the write access notification from the write circuit 1003 .

The flip-flop circuit 1005 stores 1-bit information. The register 121 has one or more flip-flop circuits 1005 as storage areas.

A port 1006 is a port (communication circuit) for the user circuit 130 to acquire the current value of the register 121 (flip-flop circuit 1005). Port 1006 is connected to user circuit 130 without going through bus circuit 1001 unlike read circuit 1002 and write circuit 1003 . Port 1006 corresponds to description 910 . In one aspect, port 1006 may be a circuit that reads data on a register 121 basis. In this case, when the data width of the register 121 is 16 bits, the port 1006 reads data in units of 16 bits. In other aspects, port 1006 may be a circuit that reads data bit by bit from register 121 .

(b. W attribute circuit example)
11 and 12, an example of a hardware description of register 121 and a circuit corresponding to the hardware description of register 121 when attribute setting item 531 has a value of "W (writable)". will be explained. It is assumed that the value of the option setting item 533 is "no option".

FIG. 11 is a diagram showing an example of the hardware description of the W-attribute register 121. FIG. A hardware description 1100 is an example of a hardware description automatically generated when the value of the attribute setting item 531 is "W (writable)" and the value of the option setting item 533 is "no option". . The hardware description 1100 is a normal hardware description (description of the W attribute (write-only) register 121), and the user circuit 130 reads the current value of the register 121 without using the bus protocol control circuit 122. contains a description 1110 of the port 1006 for

Based on the memory map, the device 100 generates a description 1110 regarding a special function circuit (a port that outputs the current value of the register 121 to the user circuit 130) other than the normal W attribute. The description 1110 makes the current value of the register 121 available to the user circuit 130 without going through the bus protocol control circuit 122 . Moreover, even if a hardware design change occurs, the device 100 automatically generates the description 1110 based on the settings input through the

screens

FIG. 12 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1100. FIG. Circuit 1200 is the circuit of W attribute register 121 . Circuit 1200 differs from circuit 1000 in the connection of read circuit 1002 . The read circuit 1002 is not connected to the flip-flop circuit 1005, and is configured to always read an initial value (or a value indicating unreadable).

In the examples of FIGS. 9 to 12, the device 100 (software 300) is configured to acquire the current value of the register 121 (flip-flop circuit 1005) even when the value of the option setting item 533 is "no option". A description of the port (communication circuit) is generated. However, if the value of option setting item 533 is "no option", device 100 does not necessarily need to generate the description of the port (communication circuit) for obtaining the current value of register 121 . In one aspect, option setting item 533 may be configured to select whether to generate a description of a port (communication circuit) for obtaining the current value of register 121 (flip-flop circuit 1005).

(c. Example of circuit with R attribute)
FIG. 13 is a schematic diagram showing an example of an R-attribute circuit. A circuit 1300 corresponds to a hardware description automatically generated when the value of the attribute setting item 531 is "R (readable)" and the value of the option setting item 533 is "no option". Unlike

circuits

1000 and 1200, circuit 1300 includes bus circuit 1001, read circuit 1002 and port 1310, but does not include write circuit 1003, flip-flop circuit 1005 and the like.

When the value of the attribute setting item 531 is "R (readable)", the device 100 outputs the value input from the special function circuit (user circuit) to the reading circuit 1002 in addition to the description of the R attribute. generate a description of the port 1310) for Many vendors provide R-attribute (read-only) circuits with ports for connecting to other circuits. At that time, hardware descriptions of ports for connecting with other circuits are added manually. On the other hand, the device 100 generates the hardware description including the description of the port 1310 through the IP-XACT file, so that the port 1310 for connecting with other circuits is independent of the hardware. description can be automatically generated. In one aspect, port 1310 may be a circuit that inputs data to registers 121 on a register-by-register basis. In this case, when the data width of the register 121 is 16 bits, the port 1310 inputs data to the register 121 in units of 16 bits. In another aspect, port 1310 may be a circuit that inputs data to register 121 for each bit of register 121 .

The hardware description of the port 1310 enables the user circuit 130 to output the value input from the user circuit 130 to the read circuit 1002 when read access occurs. In addition, the device 100 can prevent the omission of reflecting the description of the special function to the document or the circuit (hardware description) when the hardware is modified.

(d. First circuit example of "sp" option)
A first example of a hardware description of the register 121 and a circuit corresponding to the hardware description of the register 121 when the value of the option setting item 533 is "sp" will be described with reference to FIGS. 14 and 15. do.

FIG. 14 is a diagram showing a first example of hardware description of the register 121 when the value of the option setting item 533 is "sp". A hardware description 1400 is an example of a hardware description automatically generated when the value of the option setting item 533 is "sp".

The hardware description 1400 includes hardware descriptions of

ports

1501, 1502, 1503, 1504, and 1505 (see FIG. 15), which are special function circuits, in addition to normal hardware descriptions (RW attributes, etc.). The function of each port will be described later with reference to FIG. In one aspect, if the value of option setting 533 is "sp", device 100 may generate descriptions for all

ports

1501, 1502, 1503, 1504, 1505 that are special function circuits. In another aspect, the option setting item 533 may be configured so that the presence or absence of the

ports

1501, 1502, 1503, 1504, and 1505 can be individually set. In this case, the device 100 generates only the description of the port enabled by the option setting item 533 among the

ports

1501 , 1502 , 1503 , 1504 and 1505 . In another aspect, each port may be a circuit that inputs or outputs data to or from registers 121 in units of registers 121 . In this case, when the data width of the register 121 is 16 bits, each port inputs or outputs data to the register 121 in units of 16 bits. In another aspect, each port may be a circuit that inputs or outputs data to register 121 on a bit-by-bit basis.

Based on the memory map, the device 100 generates descriptions of special function circuits (at least part of the

ports

1501, 1502, 1503, 1504, and 1505) other than the normal R, W, and RW attributes. Moreover, even if a hardware design change occurs, the device 100 automatically generates a description of the special function circuit based on the settings input via the

screens

FIG. 15 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1400. FIG. A circuit 1500 is a circuit of the register 121 when the value of the option setting item 533 is "sp". Circuit 1500 comprises bus circuit 1001 , read circuit 1002 , write circuit 1003 , flip-flop circuit 1005 , and

ports

1501 , 1502 , 1503 , 1504 and 1505 .

A port 1501 is a port for outputting a value from the user circuit 130 to the read circuit 1002 . When a read access via bus circuit 1001 occurs from an external circuit, circuit 1500 outputs the value input from port 1501 to the external circuit via read circuit 1002 and bus circuit 1001 .

A port 1502 is a port for the user circuit 130 to acquire the current value of the register 121 (flip-flop circuit 1005). Port 1502 is connected to user circuit 130 without going through bus circuit 1001 . User circuit 130 can obtain the current value of register 121 without going through bus protocol control circuit 122 by using port 1502 .

A port 1503 is a port for the user circuit 130 to input an update value to the register 121 (flip-flop circuit 1005). The value of flip-flop circuit 1005 is rewritten by a signal input from port 1503 instead of a signal input from write circuit 1003 . User circuit 130 can update the value of register 121 without going through bus protocol control circuit 122 by using port 1502 .

A port 1504 is a port for notifying the user circuit 130 that write access by the write circuit 1003 has occurred. The user circuit 130 can execute arbitrary processing (such as updating the value of the flip-flop circuit 1005) when a write access occurs based on a signal obtained from the port 1504 and indicating that the write access has occurred.

A port 1505 is a port for outputting the value input by the write circuit 1003 to the user circuit 130 . User circuit 130 can execute arbitrary processing (such as processing to change the value output to port 1503 ) based on the value obtained from port 1505 .

(e. Second circuit example of "sp" option)
A second example of the hardware description of the register 121 and the circuit corresponding to the hardware description of the register 121 when the value of the option setting item 533 is "sp" will be described with reference to FIGS. 16 and 17. do.

FIG. 16 is a diagram showing a second example of the hardware description of the register 121 when the value of the option setting item 533 is "sp". A second example of the hardware description is a description obtained by adding hardware description 1600 to hardware description 1400 . The hardware description 1600 is a description regarding the port 1706 (see FIG. 17). The function of port 1706 is described below with reference to FIG.

In one aspect, if the value of option setting item 533 is “sp”, device 100 may generate hardware descriptions for all

ports

1501, 1502, 1503, 1504, 1505, and 1706, which are special function circuits. good. In another aspect, the option setting item 533 may be configured so that the presence or absence of

ports

1501, 1502, 1503, 1504, 1505, and 1706 can be individually set. In this case, the device 100 generates only the hardware description of the port enabled by the option setting item 533 among the

ports

1501, 1502, 1503, 1504, 1505, and 1706. FIG. In another aspect, each port may be a circuit that inputs or outputs data to or from registers 121 in units of registers 121 . In this case, when the data width of the register 121 is 16 bits, each port inputs or outputs data to the register 121 in units of 16 bits. In another aspect, each port may be a circuit that inputs or outputs data to register 121 on a bit-by-bit basis.

Based on the memory map, the device 100 generates a description of special function circuits (at least some of the

ports

1501, 1502, 1503, 1504, 1505, and 1706) other than the normal R, W, and RW attributes. Moreover, even if a hardware design change occurs, the device 100 automatically generates a description of the special function circuit based on the settings input via the

screens

FIG. 17 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1600. FIG. A circuit 1700 is a circuit of the register 121 when the value of the option setting item 533 is "sp". Circuit 1700 has a port 1706 in addition to the components of circuit 1500 .

A port 1706 is a port for notifying the user circuit 130 that a read access by the read circuit 1002 has occurred. The user circuit 130 executes arbitrary processing (such as processing to clear the value of the flip-flop circuit 1005 when a read access occurs) based on a signal indicating that a read access has occurred and is acquired from the port 1706 . obtain.

(f. "sn" option circuit example)
An example of a hardware description of the register 121 and a circuit corresponding to the hardware description of the register 121 when the value of the option setting item 533 is "sn" will be described with reference to FIGS. 18 and 19. FIG.

FIG. 18 is a diagram showing an example of hardware description of the register 121 when the value of the option setting item 533 is "sn". A hardware description 1800 is an example of a hardware description automatically generated when the value of the option setting item 533 is "sn". The “sn” option is an option for not including the register 121 in the memory-mapped circuit (circuit 120). If the "sn" option is enabled, device 100 generates a hardware description of the peripheral circuitry of register 121 without generating a hardware description of register 121 (one or more flip-flop circuits 1005). In addition, when the "sn" option is enabled, the device 100 hard-wires special function circuits (

ports

1501, 1502, 1503, 1504, 1505, 1706, etc.) in the same way as when the "sp" option is enabled. Generate a hardware description.

In one aspect, if the value of option setting item 533 is “sn”, device 100 may generate hardware descriptions of

ports

1501, 1502, 1503, 1504, 1505, and 1706 that are special function circuits. good. In another aspect, the option setting item 533 may be configured so that the presence or absence of

ports

Based on the memory map, the device 100 generates a hardware description regarding circuits with special functions other than the normal R, W, RW attributes. Moreover, even if a hardware design change occurs, the device 100 automatically generates a description of the special function circuit based on the settings input via the

screens

FIG. 19 is a schematic diagram showing an example of a circuit corresponding to the hardware description 1800. FIG. A circuit 1700 is the circuit of the register 121 when the value of the option setting item 533 is "sn". Circuit 1900 has

ports

1501 , 1502 , 1503 , 1504 , 1505 , 1706 similar to circuit 1700 . However, circuit 1900 does not include flip-flop circuit 1005 . Also, port 1503 is connected to port 1502 instead of flip-flop circuit 1005 .

In the case where the circuit 120 (memory-mapped circuit) includes the register 121 and the register 121 is not used, the input signal of the port 1503 needs to be treated in some way. This is because if the input voltage of the port 1503 becomes unstable or becomes an intermediate potential due to high impedance or the like, a through current may occur due to the characteristics of the CMOS circuit. Therefore, the device 100 provides an “sn” option that does not include the register 121 in the circuit 120 (memory-mapped circuit) in order to solve the problem that may occur when the circuit 120 (memory-mapped circuit) includes the register 121. provide. In one aspect, device 100 may not generate the hardware description of port 1503 itself if the "sn" option is enabled.

<E. Flowchart >
FIG. 20 is a diagram showing an example of a procedure for generating a hardware description by device 100. As shown in FIG. In one aspect, processor 201 may load a program for performing the processing of FIG. 20 from storage 203 into memory 202 and execute the program. In other aspects, part or all of the process may also be implemented as a combination of circuit elements configured to perform the process.

In step S2010, the device 100 accepts a memory map setting input. More specifically, device 100 accepts input of memory maps and settings of registers 121 included in the memory maps via

screens

400 and 500 . Register 121 settings include options for register 121 attributes, initial values, generation of special function circuits, and the like.

In step S2020, the device 100 creates a memory map including options. Device 100 generates a memory map in an arbitrary format based on settings received through

screens

400 and 500 .

In step S2030, the device 100 acquires the attribute of the register 121. More specifically, device 100 acquires the content (one of R attribute, W attribute, and RW attribute) input to attribute setting item 531 on screen 500 .

In step S2040, the device 100 acquires the initial value of the register 121. More specifically, the device 100 acquires the content input to the initial value setting item 532 (either "0" or "1" is set for each bit of the register 121) on the screen 500. FIG.

In step S2050, the device 100 acquires the option of the register 121. More specifically, on screen 500 , device 100 displays the content (“no option”, “rc”, “rs”, “sp”, “sn”, or any other option) entered in option setting item 533 . ).

At step S2060, the device 100 generates an IP-XACT (xml) file from the memory map. The IP-XACT file contains register 121 options (special features) expressed in IP-XACT format. In one aspect, device 100 may generate files of any format other than IP-XACT (xml) files from the memory map. In this case, the device 100 generates the hardware description from a file in a format other than the generated IP-XACT(xml) file.

At step S2070, the device 100 generates a hardware description from the IP-XACT file. The hardware description includes a description of the options (special functions) of registers 121 . In some aspects, device 100 may generate the hardware description directly from the memory map. In this case, the device 100 may not generate IP-XACT files.

In step S2080, the device 100 outputs the generated hardware description. In some aspects, device 100 may output only the hardware description, only the IP-XACT file, or both the hardware description and the IP-XACT file. In other aspects, device 100 may output the generated hardware description to a display connected to device 100, or may send information about the hardware description to another device.

As described above, device 100 (software 300) according to the present embodiment automatically generates hardware descriptions including descriptions of special function circuits other than descriptions relating to the R, W, and RW attributes of register 121 . By using the device 100, a user can easily design a circuit with a register 121 having a special function without using the bus protocol control circuit 122. FIG. Furthermore, since the device 100 automatically generates a hardware description including descriptions of special functions that do not use the bus protocol control circuit 122 based on the memory map options, when hardware modifications occur, the document or It is possible to prevent the omission of reflecting the description of the special function to the circuit (hardware description) or the like.

It should be considered that the embodiments disclosed this time are illustrative in all respects and not restrictive. The scope of the present disclosure is indicated by the scope of claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims. In addition, it is intended that the disclosure content described in the embodiment and each modification can be implemented singly or in combination as much as possible.

100 device, 110, 120, 140, 145, 1000, 1200, 1300, 1500, 1700, 1900 circuit, 121 register, 122 bus protocol control circuit, 130 user circuit, 201 processor, 202 memory, 203 storage, 204 output IF, 205 input IF, 206 communication IF, 207 external device IF, 208 internal bus, 300 software, 301 memory map generator, 302 IP-XACT generator, 303 hardware description generator, 400, 500 screens, 401 interface setting items, 402 Module name setting items, 403 Data width setting items, 404 Register map setting items, 405 Port setting items, 510 Address setting items, 511 Absolute address setting items, 512 Offset address setting items, 520 Register name setting items, 530 Register setting items , 531 attribute setting items, 532 initial value setting items, 533 option setting items, 700, 800, 900, 1100, 1400, 1600, 1800 hardware description, 910, 1110 description, 1001 bus circuit, 1002 read circuit, 1003 write Circuit, 1004 selector, 1005 flip-flop circuit, 1006, 1310, 1501, 1502, 1503, 1504, 1505, 1706 port.

Claims

A device for supporting digital circuit design,
a memory map generator that generates a memory map;
a hardware description generator that generates a hardware description based on the memory map;
the hardware description generation unit generates a description of a port for an external circuit to communicate with the circuit of the memory map;
The apparatus of claim 1, wherein the port description is a description of circuitry separate from write circuitry and read circuitry via a bus of registers included in the memory map.
The device according to claim 1, wherein the port description includes a port description for reading the current value of the register in units of the register.
3. The port description according to claim 1, wherein said port description includes a description of a port for inputting a value to be output to said read circuit when read processing via said read circuit occurs for said register. device.
The device according to any one of claims 1 to 3, wherein the port description includes a port description for inputting an update value to the register.
The description of the port includes description of a port for outputting a signal indicating the occurrence of the write process to the external circuit when a write process occurs to the register via the write circuit. A device according to any one of claims 1 to 4.
The device according to any one of claims 1 to 5, wherein the port description includes a port description for outputting a value input from the write circuit to the external circuit.
2. The description of said port includes a description of a port for outputting a signal indicating occurrence of said read processing to said external circuit when read processing via said read circuit occurs for said register. The device according to any one of 1-6.
further comprising an interface that accepts optional inputs for the registers;
the memory map includes the options;
The device according to any one of claims 1 to 7, wherein said hardware description generator generates a description of said port based on said option.
9. The apparatus of claim 8, wherein said options include an option to not generate said register in said memory map.
A computer-implemented method of aiding digital circuit design, comprising the steps of:
generating a memory map;
generating a hardware description based on the memory map;
generating the hardware description includes generating a description of ports for external circuits to communicate with circuits of the memory map;
The method, wherein the description of the port is a description of circuitry separate from write circuitry and read circuitry via a bus of registers included in the memory map.
A program for supporting digital circuit design,
generating a memory map;
generating a hardware description based on the memory map;
generating the hardware description includes generating a description of ports for external circuits to communicate with circuits of the memory map;
The program according to claim 1, wherein the description of the port is a description of a circuit separate from a write circuit and a read circuit via a bus of registers included in the memory map.