JPS62234290A - Memory device - Google Patents

Abstract

PURPOSE:To execute the high speed of a memory access by sending a counting-up signal only from a CPU after second word of a continuous address and counting up the address at a memory device side. CONSTITUTION:A CPU 1 mounts the first address of a continuous address to a bus 20 and sends it to an address selector 11. The selector 11 usually selects the address from the bus 20 and sends it to a RAM 12 for converting an address. After an address converted by the RAM 12 is stored into a register 13 once, the address is mounted on the bus 20 and sent to the CPU 1. Next, the CPU 1 sends a counting-up signal through a control signal line 30 and an address counter 10 counts up the address one time and sends it to the selector 11. The selector 11 selects the address from the counter 10 by a signal 25 and sends it to the RAM 12. Consequently, the number of times through the bus is decreased and the high speed is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION C. Industrial Application Field The present invention relates to a memory device used in an information processing system.

rPrior art '1 When reading data at consecutive addresses of two or more words, a conventional memory device sends the first address from the central processing unit (hereinafter referred to as CPU) to an address converter through a bus, and performs address conversion. corresponds to the specified address. Read the data in the memory and send it to the CPU through the bus. Next, send the address obtained by adding 1 to the first address from the CPU to the address converter through the bus, and read the data in the memory corresponding to the converted address.
This series of operations is repeated as many times as the number of words desired to be read is sent to the CPU via the bus. Since it has to be sent from the CPU via the CPU, the disadvantage is that it depends on the processing speed or the data, regardless of address continuity! ).

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory device which can reduce the number of addresses supplied from a PU when addressing a lotus and improve processing speed when there is continuity of addresses.

(Means for Solving the Problems) The device of the present invention retains address information supplied from Hass and uses counting software supplied from outside.

An address counter that counts up and down the address information in response to a signal, and an address counter that receives the address information supplied from the bus and the output from the address counter, normally selects and outputs the address information supplied from the bus, and outputs the address information supplied from the bus. The device includes a selection means for selectively outputting the output of the address counter in response to the supply of a count-up signal, and a storage means for outputting corresponding data to the bus in response to information supplied from the selection means. be done.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a flow diagram showing an embodiment of the present invention. 1 is CI) Ll outputs the address necessary for memory access. 10 is at the counter, holds the address sent from CI) UL, and increases the 0 account by the input signal 30 supplied from CI) (911 with alternative function). is an address selector that selects either the address input from the bus or the address input from the address counter 10. 5 12 is a random access memory (hereinafter referred to as RAM) for address conversion. 13 is a random access memory (hereinafter referred to as RAM) for address conversion. This is a register that temporarily stores the converted address.14
is a memory which inputs the address of the output of the register 13 and reads out the corresponding data. 15 is a register for temporarily storing the output of memorread 1; 20 is lotus and CP
21°22. which connects U1 and the memory device.
25 is an address signal line. 23 and 24 are data signal lines. Reference numeral 30 denotes a control signal line for sending a count signal supplied from cr'Ul to the address counter 10 and address selector 11 during continuous addressing.

Next, the operation of the professional diagram shown in FIG. 1 will be explained.

In FIG. 1, when the CPLI 1 performs memory access to consecutive addresses of two or more words, it puts the first address on the bus 20 and sends it to the address selector 11. The address selector 11 normally selects an address from the bus 20 and sends the address from the bus 20 to the address conversion RAM 12.The address converted by the address conversion RAM 12 passes through the address signal line 21 and is sent to the register 1.
3, and further passes through the address signal line 22,
In response to the supply of 8 addresses sent to memory 1 ='l, the data read from memory 1 = 1 passes through data signal line 23, is temporarily stored in register 15, and then passes through data signal line 24 to bus 20. This is placed on the CPU
L receives it.

Next, CP tJ 1 sends out the count-up "1 word" through the control signal line 30. send.

The address selector 11 selects the address input from the address counter 10 in response to the supply of the count-up signal and sends it to the address conversion RAM 12. The address converted by the address conversion RAM 12 passes through the address signal line 21 and is temporarily stored in the register 13.
Furthermore, it is sent to the memory 14 through the address signal line 22. Data read from the memory 14 in response to the supply of the address passes through the data signal line 23 and is temporarily stored in the register 15, further passes through the data signal line 24, is placed on the bus 20, and is sent to the CPU 1.

If there is a memory access request for consecutive addresses of 3 or more words, the contents of the address counter 10 are incremented by 1 and used as the address without sending the address from the CPU 1, as in the case of the 2nd word. Perform memory access.

As described above, in this embodiment, the address count I~ is performed on the memory device side, so that in the case of consecutive addresses, the number of address offerings via the bus can be reduced.

Although this embodiment describes a memory device for performing address translation, it is clear that the present invention is not limited to this.

[Effects of the Invention: 1 As explained above, when performing memory access to consecutive addresses of two or more words, the present invention allows the address necessary for the memory access from the second word onwards to be accessed via the bus.
The effect is that high-speed memory access is possible by receiving only the cursor/knob signal from the CPU without sending it from the PU, counting the address counter by 1, and sending it to the address converter. be,

[Brief explanation of drawings]

FIG. 1 is a program diagram showing one embodiment of the present invention.
11... Address selector, 12... RAM for address conversion, ]3... Register, 14... Memory,
15...Register, 2(-)...Bus, 21, 22
．． 25...Address signal line. 23, 24...Data signal line, 30.31...Control signal line,

Claims (1)

[Scope of Claims] An address counter that holds address information supplied from a bus and counts up the address information using a count-up signal supplied from the outside; selecting means for selectively outputting the address information normally supplied from the bus in response to the supply of the output, and selectively outputting the output of the address counter in response to the supply of the count-up signal; A memory device comprising: storage means for outputting corresponding data to the bus in response to information.