JPS635773B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a data conversion processing device.

In pattern information processing, etc., information processing that involves data conversion of data stored in a memory device is often performed, but in such cases, when the weight of data conversion processing becomes large, it is difficult to use the software in the data processing device. The data conversion processing time occupies a large proportion and the entire processing time becomes longer. For this reason, in conventional data conversion processing devices, a conversion circuit using hardware is separately provided and data conversion is performed by the conversion circuit, thereby reducing data conversion processing time and improving processing efficiency in the data processing section. .

However, in order to further shorten the overall processing time in the conventional device described above, it is necessary to shorten the reading time from the memory device and the data conversion time in the conversion circuit. The drawback is that it requires a large number of logic elements, resulting in an expensive device.

It is an object of the present invention to provide a data conversion system that eliminates the drawbacks of the conventional device described above and can significantly shorten the overall processing time compared to the conventional device even if the same memory elements and logic elements as the conventional device are used. The purpose of this invention is to provide a processing device.

The apparatus of the present invention includes a first storage means for storing a first type of data to be used after data conversion and a second type of data to be used without data conversion, and a first type of data supplied from a data processing apparatus. second storage means for storing parameters supplied from the data processing device in response to a parameter set signal;
Data that is converted into third type data by a parameter supplied from the second storage means in response to the supply of the first type of data from the first storage means and the supply of a third signal. a conversion means;
third storage means that receives a third type of data from the data conversion means and stores it at a designated address in response to the supply of a fourth signal; a fourth signal that is initially set to the first signal value of the value signals and stores the second signal value of the binary signals as information at a designated address in response to the supply of the fourth signal;
storage means, a second type of data from the first storage means, a third type of data from the data conversion means, and a third type of data stored in the storage means from the third storage means. When the first signal is supplied, the second type of data is selected, and when the fourth signal is supplied, the third type of data is selected from the data conversion means. data selection supply means for selecting third type of data supplied from said third storage means and supplying said data to said data processing device when said data is selected and a second signal is supplied; When the processing device supplies an address signal to the first storage means to request the second type of data, the processing device generates the first signal upon receiving a read request signal from the data processing device and processes the data. When the device supplies an address signal to the first, third and fourth storage means to request a third type of data, the fourth storage means receives a read conversion request signal from the data processing device. When the information at the designated address of the means is the second signal value of the binary signal, the second signal is generated, and when the information is the first signal value of the binary signal, the third signal is generated. and signal generating means for generating the fourth signal.

Next, the present invention will be explained in detail with reference to the drawings.

As mentioned above, with conventional equipment, whenever converted data is required, the necessary data
is read from the memory device and converted by the conversion circuit, and then the converted data Tk is supplied to the data processing section. Therefore, if one converted data Tk is used n times, If the time to read Xk from the memory device is t ₁ and the time to convert data to Tk is t ₂ , the converted data Tk
The total time until it is supplied to the data processing unit is n×
(t ₁ + t ₂ ).

However, if a separate buffer memory is prepared to store the converted data Tk, when Tk is used for the second time or later, the data Xk can be stored in the newly provided buffer memory without having to read it from the memory device again. The data conversion time is reduced by t ₂ and thus
The total supply time for n uses of Tk is the time required to read Tk from buffer memory t ₃ (this is approximately
(equal to t ₁ ), then t ₁ + t ₂ + (n-1) t ₃ ≒ nt ₁ +
t ₂ (t ₁ ≒ t ₃ ), which is (n-1) t ₂ compared to the conventional device.
The effect becomes extremely large when n is large, and the effect becomes even more significant as the number of frequently used transformation data increases.

FIG. 1 is a block diagram showing one embodiment of the present invention. One embodiment of the present invention includes a memory device 1 for storing data, and data stored in the memory device 1.
In response to the supply of conversion instruction signal _S3 in response to the supply of Xk, a certain data conversion (Tk = F (Xk, P): P is a parameter) is performed via the given parameter P, and the converted data Tk is A conversion circuit 2 that supplies
Converted data Tk converted data write signal S ₄
The conversion buffer (TRB) that stores in response to the supply of
3. Each data stored in conversion buffer 3
A directory that stores valid bits Vk that store the validity or invalidity of Tk in response to the supply of the conversion data write signal _S4 , and sets all Vk to "0" in response to the supply of the parameter set signal PS. 4 (Tk is valid when Vk is “1”,
(Tk is invalid when Vk is "0"), in response to the supply of signal S1 from the timing generator 90, which will be described later, in response to data being supplied from the memory device 1, conversion circuit 2, and conversion buffer ₃ . a switching circuit 5 for selecting data from the memory device 1, selecting data from the conversion buffer 3 in response to the application of the signal _S2 , and selecting data from the conversion circuit 2 in response to the application of the signal _S4 ; , a parameter register 6 that stores parameters P necessary for data conversion in response to the supply of a parameter set signal PS, a data processing device 7 that performs data processing, and a conversion register (TRR) that temporarily stores data Xk that requires conversion. ) 8, a read register 9 that temporarily stores the supplied data in response to the supply of the data set signal S ₀ , various timing pulses (S ₀ , S ₁ , S ₂ ,
The timing generating section 90 generates timing signals ( _S4, etc.).

Address signals for writing and reading data to and from the memory device 1, conversion buffer 3, and directory 4 are assigned entry numbers Mk (K=0 to n-
1 natural number) and word number Wl (l = 0, 1)
It consists of FIG. 2 is a layout diagram showing the data storage state of the memory device 1, where Xk, that is, data that requires conversion, is stored at address (Mk, W ₀ ), and Ak, that is, data that requires conversion, is stored at address (Mk, W ₁ ). Data that does not exist is stored. FIG. 3 is an address signal path diagram for memory access in FIG. Only Mk is used, and both are supplied from the data processing device 7 via the address line 50 to designate the address for writing or reading data.

Next, the operation of the embodiment will be explained with reference to FIG.

In the initial state, the data necessary for data processing
X ₀ to _{X o-1} and A ₀ to A _o-1 are stored in the memory device 1 in the arrangement shown in FIG. 2 above. Next, the parameter P is supplied from the data processing device 7 to the parameter register 6, and a parameter set signal is generated.
Parameter P is set in parameter register 6 in response to the supply of PS. Also directory 4
In response to the supply of the parameter set signal PS to the directory 4, all bits of _V0 to Xo _-1 stored in the directory 4 are cleared and set to "0".

In this state, data necessary for processing is read from the memory device 1, and some data is converted and supplied to the data processing device 7, where the processing proceeds. Whether the data supplied to the data processing device 7 is data Ak that does not require conversion or converted data Tk, and in the latter case, whether Tk is supplied from the conversion buffer 3 or whether Xk is converted to Tk. conversion circuit 2
Since there are three cases in total, each case will be explained separately.

a When Ak is supplied Address signals (Mk,
W ₁ ) is supplied to the memory device 1 and the address (Mk,
Ak stored in W ₁ ) is read out and supplied to the switching circuit 5. In response to the supply of the signal S ₁ from the timing generator 90, the switching circuit 5 selects Ak and supplies it to the read register 9, and the read register 9 responds to the supply of the data set signal S ₀ from the timing generator 90. and set Ak.

b When converted from Xk to Tk and supplied Address signal (Mk,
W ₀ ) is supplied to the memory device 1 and the address (Mk,
Xk stored in W ₀ ) is read out and supplied to the conversion circuit 2. Further, an address signal (Mk) is supplied from the data processing device 7 to the directory 4, and data Vk stored at the address (Mk) is read out and supplied to the timing generation section 90.
Vk = “0” (In directory 4, all Vk are reset to “0” by parameter set signal PS)
Therefore, the conversion instruction signal S ₃ is supplied from the timing generation section 90 to the conversion circuit 2. In response to the supply of the signal _S3 , the conversion register 8 stores Xk, the conversion circuit 2 starts the conversion operation, and converts Xk into the parameter P.
The converted data Tk is created through the converter 5 and is supplied to the switching circuit 5 and the conversion buffer 3. Next, a conversion data write signal is generated from the timing generator 90.
_S4 is supplied to the conversion buffer 3, directory 4 and switching circuit 5. The switching circuit 5 selects Tk supplied from the conversion circuit 2 via the data line 20 in response to the supply of the signal S ₄ and supplies it to the read register 9. The read register 9 stores Tk in response to the data set signal _S0 supplied from the timing generator 90. Conversion buffer 3 is a signal
In response to the supply of the signal _S4 , the directory 4 stores the Tk supplied from the conversion circuit 2 at the address Mk specified by the address signal (Mk) supplied via the address line 50, and the directory 4 supplies the signal _S4 . In response to this, Vk at the address specified by the address signal (Mk) supplied is rewritten to "1", and preparations are made to indicate that it is valid in response to subsequent inquiries regarding the validity of Tk for directory 4. do.

c. When Tk is supplied from the conversion buffer 3 In this case, Xk has already been read once, converted to Tk and used, and Tk is stored in the conversion buffer 3, and Vk="1". An address signal (Mk) is supplied from the data processing device 7 to the directory 4 and conversion buffer 3. The directory 4 reads data Vk at the address Mk specified by the address signal (Mk) and supplies it to the read timing generator 90. Conversion buffer 3 converts the address in response to the supply of the address signal (Mk).
Tk stored in Mk is read and supplied to the read switching circuit 5. The timing generator 90 has Vk=
Since it is "1", the signal _S2 is supplied to the switching circuit 5, and in response to the supply of the signal _S2 , the switching circuit 5 selects Tk supplied from the conversion buffer 3 and supplies it to the read register 9. , the read register 9 stores Tk in response to the data set signal _S0 supplied from the timing generator 90.

Signals S ₀ to _{S 4} that control the above operations are generated by the timing generator 90. FIG. 4 is a circuit diagram of the timing generator 90, and FIG. 5 is a time chart showing its operation in relation to the operation of FIG. 1.

The counter 101 is a time generating circuit, and the time _t3 from when it is activated until a logic "1" appears on the connection line 201 is sufficient time to read the data Tk from the conversion buffer 3, and a logic "1" appears on the connection line 202. The time t ₁ until the data appears from memory device 1
Sufficient time to read Ak and connection line 203
The time _t4 until logic "1" appears in the memory device 1 is sufficient time to read the data Xk from the memory device 1, convert it in the conversion circuit 2, and supply Tk to the switching circuit 5 (this is the time _t4 described above). +t ₂ ). Counter 101 is reset by receiving a logic "0" from AND gate 120. Flip flop 102, 10
3 and 104 are set when a logic "1" is supplied to the S terminal, and reset when a logic "0" is supplied to the R terminal. In the initial state, all flip-flops are in the reset state and the counter 10 is
1 has also been reset.

For convenience, if () Ak is supplied, () if Tk is supplied from conversion buffer 3, then ()
The following will explain the case in which Xk is converted to Tk and supplied to the data processing device 7. (), (), () in the time chart in Figure 5 are based on this.

() When Ak is supplied The read request signal RDRQ (logic “1” pulse) for reading Ak from the data processing device 7 is supplied to the timing generation circuit 90 and the counter 101
and set the flip-flop 102.
The connection line T becomes logic "1", and after a time _t1 sufficient to read Ak, the connection line 202 becomes logic "1".
pulse is given. As a result, a logic "1" signal _S1 via the NAND gate 114 and the inverter 111 and a logic "1" data set signal _S0 via the NAND gate 114 and the NAND gate 116 are supplied to the outside, and the read register (DR) is supplied. Data Ak is stored in 9. In addition, a logic "0" is supplied to the counter 101 via the NAND gate 114 and the AND gate 120 to reset the counter 101. Furthermore, Nand Gate 11
4 and logic “0” through AND gate 118
is applied to the R terminal of flip-flop 102 to reset flip-flop 102.

() When Tk is supplied from the conversion buffer The read and conversion request signal RTRQ (pulse of logic “1”) for reading the conversion data Xk from the data processing device 7 is supplied to the timing generation circuit 90 and the counter 101 and sets flip-flops 102 and 103. Connecting lines T and _C1 become logic “1” and conversion buffer 3
After a time t ₃ sufficient to read Tk from , a logic "1" pulse is applied to connection line 201. Note that during this time, Vk read from the directory 4 is given to the timing generator 90.
Vk is logic "1". After connection 201, a logic "1" S2 signal is applied via NAND gate 115 and inverter 110, and a logic "1" _S2 signal is output via NAND gate 115 and NAND gate 116 in response to the supply of a logic "1" pulse to 201. S ₀ signal is supplied externally and read register (DR) 9
The data Tk stored in the conversion buffer 3 is stored in . A logic "0" is also supplied to counter 101 via NAND gate 115 and AND gate 120 to reset counter 101. Further, a logic "0" is supplied to the R terminal of the flip-flop 102 via the NAND gate 115 and an AND gate 118, and a logic "0" is supplied to the R terminal of the flip-flop 103 via the inverter 108.
and reset 103.

() When Xk is converted and supplied to Tk The read and conversion request signal RTRQ (pulse of logic “1”) for reading the conversion data Xk from the data processing device 7 is supplied to the timing generation circuit 90. Start counter 101 and set flip-flops 102 and 103. After connection, T and _C1 become logic “1” and conversion buffer 3
After a time t ₃ sufficient to read Tk from , a logic "1" pulse is applied to connection line 201. Note that during this time, Vk read from the directory 4 is given to the timing generator 90. This time, Vk is at logic "0". Therefore, in response to a logic "1" pulse applied to connection line 201, flip-flop 104 is set via AND gate 117, and logic "0" is supplied to the R terminal of flip-flop 103 via inverter 108. Only flip-flop 103 is reset. A logic "0" is applied to the connection line _C1 , and a logic "1" is applied to the connection line _C2 .
Logic "1" is still applied to the connection line T. This means that the requested data Tk is no longer in the conversion buffer 3, and Xk is still being read from the memory device 1. Then, after a time t ₁ sufficient to read out Xk, a logic "1" pulse is applied to connection line 202. In response to the supply of this pulse, a logic "1" conversion instruction signal _S3 is supplied to the outside (conversion circuit 2) via the AND gate 119, Xk is stored in the conversion register (TRR) 8, and the conversion operation is started. be done. Also Nand Gate 11
A logic ``0'' is applied to the R terminal of flip-flop 102 through 4 and AND gate 118 to reset flip-flop 102. Then, after a time (t ₁ +t ₂ ) sufficient for Xk to be converted to Tk and supplied to the switching circuit 5, a logic "1" pulse is applied to the connection line 203. In response to the supply of this pulse, a conversion data write signal _S4 of logic "1" is outputted via the AND gate 121, the AND gate 121, the inverter 112 and the NAND gate 1.
A data set signal _S0 of logic "1" is supplied to the outside via the input terminal 16, Tk is set in the read register (DR) 9, and the address of the conversion buffer (TRB) 3 is set.
Tk is written to Mk, and Vk at address Mk in directory 4 is rewritten from logic "0" to logic "1". Furthermore, and gate 121,
Logic "0" is supplied to the counter 101 via the inverter 112 and the AND gate 120 to reset the counter 101, and the AND gate 121 and
Flip-flop 10 via inverter 112
A logic "0" is applied to the R terminal of the flip-flop 104 to reset the flip-flop 104.

In this embodiment, when using the conversion-required data Xk, Xk is converted to Tk only at the first use.
Store the converted data Tk in the conversion buffer 3, and when using it for the second time or later, use the Tk stored in the conversion buffer 3 instead of reading out Xk again and converting it to Tk. Therefore, when using Tk from the second time onwards, the time _t2 required for the conversion each time can be shortened compared to conventional equipment without using particularly high-speed circuit elements, and the overall processing can be significantly reduced. It can save time.

As described above, by using a conversion buffer for storing converted data, the present invention can significantly reduce processing time compared to conventional devices even if the same memory elements and logic elements as conventional devices are used. It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 is a layout diagram showing the data storage state of the memory device in Figure 1, Figure 3 is an address signal path diagram for memory access in Figure 1, and Figure 4 is a circuit diagram of the timing generator in Figure 1. 5 is a timing chart showing the operation of FIG. 1. In the figure, 1... Memory device, 2... Conversion circuit, 3... Conversion buffer (TRB), 4... Directory, 5... Switching circuit, 6... Parameter register, 7... Data processing device, 8 ...Conversion register (TRR), 9...Read register (DR),
10, 20, 30, 40, 60, 70...data line, 50...address line, 90...timing generator, 101...counter, 102-104...
Flip-flop, 106-112...Inverter, 113-116...Nand gate, 117-
121...And gate, _M0 to M _o-1 ... Entry number, _W0 , _W1 ... Word number, _X0 to _{X o-1} ,
A ₀ ~A _o-1 , T ₀ ~ _{T o-1} ...data, V ₀ ~ _{V o-1} ...
Valid bit, RDRQ...read request signal,
RTRQ...Read conversion request signal, PS...Parameter setting signal, T, _C1 , _C2 , _C3 ...Connection line, _S1 ,
_S2 ...Switching signal, _S3 ...Conversion instruction signal, _S4 ...Conversion data write signal, _S0 ...Data set signal.

Claims (1)

[Claims] 1. A first storage means for storing a first type of data to be used after data conversion and a second type of data to be used without data conversion; a second storage means for storing parameters supplied from the data processing device in response to a parameter set signal sent from the first storage means; data conversion means for converting the data into a third type of data using parameters supplied from the second storage means in response to the supply of data; a third storage means for storing at a designated address in response to the supply of the parameter set signal; fourth storage means for storing a second signal value of the binary signal as information at a designated address in response to the supply of the signal; and a fourth storage means for storing the second type of data from the first storage means and the When receiving the third type of data from the data conversion means and the third type of data stored in the storage means from the third storage means and receiving the first signal, the second When the type of data is selected and the fourth signal is supplied, the third type of data supplied from the data converting means is selected and when the second signal is supplied, the third storage data selection and supply means for selecting a third type of data supplied from the means and supplying it to a processing device;
When requesting the second type of data by supplying it to the storage means of the data processor, the data processor generates the first signal in response to the read request signal supplied from the data processor, and the data processor transmits the address signal to the first, When requesting the third type of data by supplying it to the third and fourth storage means, the information at the specified address of the fourth storage means is Generating the second signal when the information is a second signal value of the binary signal, and generating the third signal and the fourth signal when the information is a first signal value of the binary signal. A data conversion processing device comprising: signal generation means.