JPS63255749A - Memory system - Google Patents

Abstract

PURPOSE:To realize an efficient and large-capacity memory system while keeping the software compatibility with a conventional extended memory by adding a map register, in which mapping information including set information supplied from a CPU is stored, to the memory system. CONSTITUTION:Arbitrary data (D0-D7) is written from a CPU (omitted in the figure) to a page control register 210. Simultaneously, a page selecting signal and a set selecting signal are generated in accordance with the address (A0-A15) from the CPU by a read/write control circuit 200, and data, which is obtained by adding data from 0 data 231 and BA data 232 and data D0-D6 by an adding circuit 230, and data D7 are written in a map register 250 selected by the page selecting signal. When the memory access to a page frame is performed by the CPU, a memory chip 290 is accessed by the address generated in an address synthesizing circuit 270 by the output from the map register 250 corresponding to a designated physical page and the address A0-A13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objectives of the Invention] (Field of Industrial Application) The present invention relates to a memory system including an extended memory of the LIM method, which is one of the extended memory methods.

(Prior Art) In recent years, the memory 82 of personal computers has tended to increase, and various types of memory systems have been proposed. LIH type expansion memory is a type of expansion memory.
This method uses a part of the CPU's memory address space as a window, and accesses up to 8MB of memory through the window. LIM is the United States! , otus/Intel/Mic
This is a method in which the three companies jointly announced the specifications, and a well-known example of a product is the Above board made by Yoneguchi's former NTC1 company.

FIG. 11 shows the memory relationship. Extended memory window is I
[4 in a row at around 1Kr311t. The 18KB window is called a physical page, and the four physical pages together are called a page frame. Further, the extended memory accessed from each physical page is also 16 KB and 11th in size, and is called a logical page.

There are a maximum of 512 logical pages, and the total capacity is 16K.
BX 512-8MB. The correspondence between physical pages and logical pages is done by the CPU by changing the contents of an I/O port called a page control register.
u can access up to 8MB of memory in total.

FIG. 12 shows a conventional system block diagram.

Each expansion memory has a set number, each corresponding to an I/O port address of the page control register. There are four page control registers in each extended memory. Physical page Y1 set X (X-0,1,5,
B Y=0.1, 2.3) 0) The page control register has the format shown in FIG. In the figure, each bit has the following meaning.

PE: Page enable bit 0; disabled Mapping of physical page Y to logical page is not performed within the range of logical pages of set X.

1; Mapping of enabled physical page Y to logical page is performed within the range of logical pages of set X.

PAi: Page address bit Specifies the logical page to which physical page Y is mapped. PE-
When it is 0, it is invalid.

Next, to explain the operation, CPU110 connects to the standard (convention) via the system bus 120.
al) Memo January 30, Extended memory 140, Expanded memory 8/O~84
0 respectively.

When accessing extended memory 8/O to 840, input any value to page control registers 811 to 841 in advance.
Set by /O light.

Now, assume that physical page Y is mapped to logical page Z. Kokote, Y-0, 1, 2, 3, Z-0, 1,..., 5
It becomes 12. First, determine which set X logical page Z is on. Here, it is assumed that X-0, 1, 5, and 6.

Next, the offset of set X of logical page Z within the logical page range is determined. This offset is set as PAl, and the 8bH data set as PC-1 is transferred to page Y1 by the CPU.
I/O write to page control register of set X. At the same time, 8-bit data set as PE-0 is I/O written to the page control register of page Y of another set.

Note that PA+ is optional. After setting data in the page control register, when CPUll0 performs memory access to physical page Y, the page control register 81
Among the memory chips 1 to 841, only set X, which is PE-1, is selected, and memory access is performed to the corresponding memory chip among the memory chips 813 to 843.

(Problems to be Solved by the Invention) Advances in semiconductor technology have made it possible to use highly integrated memory chips. 30, it has become possible to integrate all of the expansion memories 140 into one system board.

At that time, the conventional method of condensing the circuit as is onto the system board had the disadvantage that the control circuit became complicated and the cost increased.

For extended memory, the page control register P
It is also possible to consider a method in which the bit length of A is increased from 7 bits to 9 blts and all 512 logical pages are controlled by one page control register. However, in this method, the page control register seen from the software is different from the conventional method, and there is a problem with software compatibility.

The present invention has been made based on the above drawbacks, and by introducing a new concept of a map register, it is possible to realize a highly efficient and large capacity expanded memory while maintaining software compatibility with conventional expanded memory. The purpose of the present invention is to provide a memory system including standard memory and expandable memory.

[Structure of the Invention] (Means for Solving the Problems) The expansion memory of the present invention maintains software compatibility with conventional expansion memories, achieves high efficiency and large capacity, and can also be used as a mark memory and an expansion memory. This configuration realizes a memory system including the following. Therefore, conventionally, this type of device has a page control register, a read/write control circuit, a decoding circuit, an address synthesis circuit, a memory control circuit, and a memory chip. a conversion circuit for converting into mapping information including set information to represent; a map register for storing mapping information including set information supplied from the CPU and the conversion circuit; and a standard memory and an expansion memory from addresses supplied from the CPU. an address detection circuit for detecting the address of the CPU; and a selection circuit for selecting either the mapping information supplied from the map register or the address supplied from the CPU based on the data supplied from the address detection circuit; An arithmetic circuit for generating a memory access permission signal from data supplied from an address detection circuit and the map register is added.

(Function) In the above (1M configuration), the page control register stores mapping information for the extended memory section.The conversion circuit
Converts the data supplied from the server into mapping information including set information. The map register stores mapping information including set information. The read/write control circuit controls I/O reads and writes to the page control register and I/O writes to the map register. The decode circuit determines the physical frame number within the page frame φ address. The address detection circuit detects addresses of the marker memory and expansion memory. The selection circuit selects the map
Either the mapping information supplied from the register or the address supplied from CPtJ is selected. The address synthesis circuit synthesizes the data supplied from the selection circuit and the lower address of the system bus address. The arithmetic circuit generates a memory access permission signal. The memory control circuit performs memory access according to a memory access address, a memory read/write signal, and a memory access permission signal. Data is output to the memory chip according to a memory control signal and a memory chip address.

This makes it possible to realize highly efficient, large-capacity expanded memory while maintaining software compatibility with conventional expanded memory, and to realize a memory system that also includes standard memory and expansion memory.

(Example) An example of the present invention will be described below with reference to the drawings. FIG. 1 is a system block diagram illustrating one embodiment of the present invention. In the figure, the I/O is the CPU, 1
20 is a system bus.

130 is a memory or a system. System-Memory 1
30, a page control register 131, a map register 132, a memory control circuit 133, and a memory chip 134;
It is configured with CPUll through the system board 120.
Connected to 0. The page control register 131 is the page control register 811, 821, 831, 841 in FIG.
The format is the same as that of the system shown in FIG. 12, and there are <16 pieces. There are four map registers 132 corresponding to four physical pages, and each map register is 11 bits long. Map of page Y (Y-0, 1, 2, 3)
The register has the format shown in FIG. In the figure, each bit has the following meaning.

ME; map enable bit 0; disabled The mapping of the physical page Y to the logical page is not performed in the system φ memory of FIG.

1; Enable Physical page Y is mapped to a logical page in the system memory of FIG.

MAi: Map address bits (i-14 to 23)
Specifies the logical page that maps the physical page. It is invalid when the liver is -0.

In the case of ME-0, the extended memory is not used at all, or is used for a mixed configuration with conventional extended memory. Since there are 512 logical pages from 0 to 511, any logical page can be specified from among the 512 logical pages using 9 bits. However, since the memory access address allocated to the extended memory does not start with O, MAi requires 1 obiL. Furthermore, the map register 132 is not directly visible from CPtJllO, but a total of 16 page control registers are visible as before. Writing to map register 132 is performed by the CPU.
Writing to page control register 131 by ll0 (I
/O write).

Now, when the CPU 11O writes data in the format shown in FIG. 13 to the page control register of page Y and set written, and thereafter the CPU
The data is read by I/O read by ll0.

(2) At the same time, ME-PE, MAi=PA(
i-14)+BAi (i-14 to 23) and the data shown in FIG. 4 are written. However, PA9-PA8
-PA7-0, and BAi(]=14 to 23) is the fixed data shown in FIG. 5 when the standard memory has a fli40KB configuration, and when the standard memory has a 512KB configuration,
This is fixed data shown in FIG.

MAi also contains set X information, but the PA bit in the page control register only represents the logical page number offset for each set X.

BAi is the value for logical pages whose logical page number offset is 0 for the four sets, ie, logical pages 0, 128, 256, and 384. Also,
It can also be considered as the upper/Obit of the starting address for each set of extended memory areas in the memory access address space. It is important here that the addition is performed when writing to the map register.

Normally, data in the map register is stored in page φ by the CPU.
Read when reading or writing memory through a frame. Addition may be performed at the time of reading, but in this case, the speed of memory access decreases due to the time required for addition, but in this embodiment,
Since the addition is performed when writing to the map register, there is no speed reduction. FIG. 2 shows a block diagram of one embodiment of the present invention. In the figure, 121 is a data bus, 122 is an address bus, and connects CPUll0 and memory system 13.
Connect 0. 200 is a read/write control circuit, which connects signal lines 201 and 20 to the address bus 122.
Connected via 2. 2/O is a page control register and is connected to the data bus 12 via signal line 211.
1 is connected to the read/write control circuit 200 via a signal line 203.

220 and 221 are decoding circuits. Decode circuit 2
20 is connected to the address bus 122 via a signal line 222. A decode circuit 221 is connected to the decode circuit 220 via a signal line 224 and to the address bus 122 via a signal line 223. 230, 231.232 are conversion circuits, 23
0 is an adder circuit, 231 is 0 data, and 232 is BA data. Summing circuit 230 connects the data bus! via signal line 233 to the data bus! 22 is connected to the 0 data 231 via a signal line 234 and to the HA data 232 via a signal line 235, and the BA data 232 is connected to the read/write control circuit 20 via a signal line 205.
Connected to 0. 240 is an address detection circuit;
It is connected to the address bus 122 via a signal line 241. 250 is a map register, which is connected to the read/write control circuit 200 via the signal line 204.
to the data bus +21 via signal line 251.
to the adder circuit 230 via a signal line 236;
It is connected to the decoding circuit 221 via a signal line 225. 260 is a selection circuit, and the signal line 252
to the map register 250 via signal line 2
62 to the address bus 122 and signal line 242 to the address detection circuit. 2
61 is an arithmetic circuit, which is connected to the map register 250 via a signal line 253 and to the address detection circuit 240 via a signal line 242. 270 is an address synthesis circuit, which is connected to the address bus 122 via a signal line 271 and to the selection circuit 260 via a signal line 2B3. 280 is a memory control circuit, which is connected to the arithmetic circuit 2 via a signal line 264.
61 is connected to the address bus 122 via a signal line 281 and to the address synthesis circuit 270 via a signal line 272. Reference numeral 290 denotes a memory chip, which supplies the data to the memory control circuit 280 via signal lines 282 and 283 and the data via a signal line 291.
Connected to bus 121.

Figure 7 shows the C of a system in which there is a part that is decompression memory and extended memory, and the standard memory is 640KB.
FIG. 3 is a diagram showing the relationship between a PU's memory contention address space and memory access address space.

Figure 8 shows the C of a system in which there is a part that is decompression memory and extended memory, and the standard memory is 512 KB.
FIG. 3 is a diagram showing the relationship between a PU's memory address space and memory access address space. FIG. 9 is a diagram showing the relationship between the memory address space and memory access address space of the CPU in a system in which no expansion memory exists and the standard memory is 640 KB. FIG. 1O is a diagram showing the relationship between the memory address space of the CPU and the memory access Φ address space in a system in which there is no expansion memory and the standard memory is 512 KB. In either case, the map register MAi holds the upper 24-bit address/Obit of the address space on the right side of each figure, that is, the memory access address space.

In the case of FIGS. 7 and 8, the use of the expanded memory and decompression memory is managed by software.

The operation of the embodiment of the present invention will be described in detail below.

cputto inputs/outputs arbitrary data (Do to D7) to the page control register 2/O via the signal line 211.
Write by O write. At the same time, the read/write control circuit 200 receives a signal from the CPUILO via the signal line 202.
According to the control signal supplied via the signal line 20
A page selection signal and a set selection signal are generated from the address (AO to Δ15) supplied via 1. Of the map register 250, read/write control circuit 2
CPUll0
The data (D7) supplied via the signal line 251
) and data (MAi) supplied from the adder circuit 230 via the 1d line 236 are written. Here, data (MAj) is PA supplied from 0 data 231.
9. PA8. Data O corresponding to PA7, BAI supplied from BA data 232, and data (Do to D6) supplied from CPUll0 via signal line 233.
) is the data added by the adding circuit 230. C.P.
When U11.0 performs a memory access to a page ψ frame, it accesses the map corresponding to the specified physical page.
Register 250 is selected by each signal. At the same time, the address detection circuit 240 sets the detection signal to 0 because the page frame address is neither a standard memory address nor an expanded memory address. As a result, the signal HIE supplied from the map register 250 via the signal line 253 is supplied to the memory control circuit 280 via the arithmetic circuit 261 to control permission/prohibition of memory access. The address synthesis circuit 270 uses data (MAi) supplied from the map register 250 via the signal line 252 as an upper address, and uses data (AO to A13) supplied from the CPU110 via the signal line 271.
) are combined and supplied to the memory control circuit 280 via the signal line 272 as a memory access address. The 24-bit memory access address is AO
~A13. The addresses are MA14 to MA23.

By changing the data applied to page control register 2/O, CPUll0 simultaneously controls map register 250.
You can check the basic history of the data. In other words, memory chip 290
It is possible to permit/prohibit access to and history of memory addresses. However, the memory access address can only be changed within a preset extended memory area. When viewed from CPUll0, the image is exactly the same as when four conventional expansion memory boards are mounted.

Next, a case will be described in which the CPU IO, standard memory, and expansion memory are accessed. First, a detection signal] is output from the address detection circuit 240, and 1 is supplied from the arithmetic circuit 261 to the memory control circuit 280 via the signal line 253, allowing 1M memory access. The selection circuit 260 selects the data (A14 to A23) supplied from crt+1to via the signal line 262, and supplies it to the address synthesis circuit 270 via the signal line 263. The address synthesis circuit 270 then processes the data (Al
1 to A23) as the upper address, and data (AO to ^1) supplied from CPUll0 via the signal line 271.
3) is used as a lower address and a memory access address is synthesized. The 24-bit memory access addresses are addresses AO to A23. This is equivalent to the CPU's memory access address, and is exactly the same image as when accessing conventional standard memory and expansion memory. The memory control circuit 280 includes the memory chip 29
0, the memory access address is supplied from the address synthesis circuit 270 via the signal line 272, regardless of whether it is standard memory, expanded memory, or expanded memory, and the memory is supplied via the signal line 264 from the arithmetic circuit 261.・Access permission signal, signal line 2 from CPUll0
According to the memory read/write signal supplied via the memory chip 81, a memory chip address and a memory control signal are generated, and the memory chip 290 is accessed.

Note that in this embodiment, the page frame address is fixed. Like the Above board from Intel1, it can also be applied to a system in which the page frame address is variable. Furthermore, although the case where four conventional expansion memories are combined into one memory has been described, it is also possible to combine one, two, or three conventional expansion memories into one memory. In that case, one, two, or three sets of page control registers will be prepared. In this embodiment, the memory configurations shown in FIGS. 7, 8, 9, and 0 are explained, but other memory configurations can be supported by changing the decoding circuit and B^data. .

With these T and l, standard memory, expansion memory, and multiple expansion memories, which conventionally had separate control systems and memory chips, can be realized as a memory system with the same memory control system and the same memory chip. can. Since there is no need to read the page control register data when the CPU accesses the memory, the memory control circuit is required less than the memory that determines the memory access address and permission for memory access after reading PE and PA. speed is reduced. Memory when accessing extended memory
Since the addition to determine the access address is performed when writing data to the map register, the addition is performed in the map register.
Compared to memory, which is used when reading data from registers, memory can be accessed faster. Software-wise, it is compatible with conventional memory systems.

Conventionally, even if IMB is implemented as standard memory, 640
384KB for KB configuration, 512 for 512KB
Kr3 could not be used and was wasted, but in the present invention, it can be used as an extended memory. Can be mixed with conventional expansion memory boards and expansion memory boards. Even if the number of memory chips mounted on the board is small and the capacity is small,
Expansion is easy by simply adding memory chips, so an expansion memory of 8M+3/board can be achieved.

[Effects of the Invention] As explained above, according to the present invention, a maximum of 8M13 expansion memories can be realized on one board while maintaining compatibility between conventional expansion memories and software.
This has the advantage that a memory system including expansion memory can be realized.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 3 is a diagram showing the format of the map/° register in FIG. 1.
Figure 4 shows the upper 2 bits of the page control register in Figure 1 and the set number, and Figures 5 and 6 show the upper IO bits and set number of the map register in Figure 1. 1, FIG. 7, FIG. 8, FIG. 9, and FIG. 13 is a diagram showing a conventional example, and FIG. 13 is a diagram showing the format of the page control register shown in FIG. 12. 200...Page control register 2/O...Read/write control circuit 220.221...Decode circuit 222...Address detection circuit 230...Addition circuit 231...0 data 240...BA Data 250...Map register 260...Selection circuit 261...Arithmetic circuit 270...Address synthesis circuit 280...Memory control circuit 290...Memory chip

Claims (1)

[Claims] Defining a part of the address space of the CPU as a window,
In an information processing device that accesses expanded memory to which set numbers are assigned to each of a group of memory blocks to which page numbers are assigned through this window, pages of memory blocks in which data supplied from the CPU are stored are stored. A page control register that stores mapping information, which is information representing a number; and a page control register that stores mapping information, which is information representing a number; A conversion circuit for converting, a map register for storing mapping information including set information supplied from a CPU and the conversion circuit, and an I/O write to the page control register, an I/O O lead and said map
A read/write control circuit that controls I/O writes to registers, a decoding circuit that detects the page frame address from the memory address supplied from the CPU and obtains the physical page number, and a decoding circuit that detects the page frame address from the memory address supplied from the CPU, and an address detection circuit for detecting addresses of standard memory and expansion memory; and mapping information or CP supplied from the map register by data supplied from the address detection circuit.
a selection circuit that selects either one of the addresses supplied from the U; an address synthesis circuit that synthesizes the data supplied from the selection circuit and a lower address of the system address supplied from the CPU; and the address detection circuit. an arithmetic circuit that generates a memory access permission signal from data supplied from the arithmetic circuit and the map register; and a memory access permission signal supplied from the arithmetic circuit and a memory access address supplied from the address synthesis circuit. and a memory control circuit that accesses the memory according to memory read/write signals supplied from the CPU; and data input/output is performed according to the memory control signal and memory chip address supplied from the memory control circuit. A memory system comprising a memory chip.