JPS62117796U - - Google Patents
Info
- Publication number
- JPS62117796U JPS62117796U JP469886U JP469886U JPS62117796U JP S62117796 U JPS62117796 U JP S62117796U JP 469886 U JP469886 U JP 469886U JP 469886 U JP469886 U JP 469886U JP S62117796 U JPS62117796 U JP S62117796U
- Authority
- JP
- Japan
- Prior art keywords
- data
- parallel
- output
- circuit
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Information Transfer Systems (AREA)
Description
第１図は本考案による並列入力直列出力メモリ
回路の実施例を示す回路図、第２図は第１図の各
部信号の書込時の波形図、第３図は第１図の各部
信号の読出時の波形図、第４図は従来の並列入力
直列出力メモリ回路のブロツク図である。
１，５…Ｎ×Ｍメモリ・アレイ、２，６…デー
タ・バス、３，７…アドレス・バス、４，８…制
御回路、９…並列直列変換回路。
Fig. 1 is a circuit diagram showing an embodiment of the parallel input serial output memory circuit according to the present invention, Fig. 2 is a waveform diagram of each part signal in Fig. 1 during writing, and Fig. 3 is a waveform diagram of each part signal in Fig. 1. FIG. 4 is a block diagram of a conventional parallel input serial output memory circuit. 1, 5...N×M memory array, 2, 6...data bus, 3, 7...address bus, 4, 8...control circuit, 9...parallel-serial conversion circuit.
Claims (1)
テムにおけるデータの並直列変換する回路におい
て、書込時、並列データに同時に書込信号を、読
出時、クロツクに同期させた読出信号を出力する
制御回路と、システムのデータバスとアドレスバ
スに接続され、メモリ素子の出力のすべてを布線
論理和接続して前記制御回路の出力によつて書込
み、読出しをする、１ビツト×Ｌ語の容量を持つ
Ｎ×Ｍメモリアレイとからなり、並列データを直
列に出力するように構成したことを特徴とする並
列入力直列出力メモリ回路。 In a circuit for parallel-serial conversion of data in a computer system that often processes parallel-serial conversion of data, a control circuit that simultaneously outputs a write signal for parallel data when writing and a read signal synchronized with a clock when reading. , is connected to the data bus and address bus of the system, and has a capacity of 1 bit x L words, and is written and read by the output of the control circuit by wire-OR-connecting all the outputs of the memory elements. 1. A parallel input serial output memory circuit comprising a ×M memory array and configured to output parallel data in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP469886U JPS62117796U (en) | 1986-01-17 | 1986-01-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP469886U JPS62117796U (en) | 1986-01-17 | 1986-01-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62117796U true JPS62117796U (en) | 1987-07-27 |
Family
ID=30785598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP469886U Pending JPS62117796U (en) | 1986-01-17 | 1986-01-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62117796U (en) |
-
1986
- 1986-01-17 JP JP469886U patent/JPS62117796U/ja active Pending
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