JPS60123051U - shared memory controller - Google Patents
shared memory controllerInfo
- Publication number
- JPS60123051U JPS60123051U JP527484U JP527484U JPS60123051U JP S60123051 U JPS60123051 U JP S60123051U JP 527484 U JP527484 U JP 527484U JP 527484 U JP527484 U JP 527484U JP S60123051 U JPS60123051 U JP S60123051U
- Authority
- JP
- Japan
- Prior art keywords
- shared memory
- storage device
- memory controller
- select signal
- central processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Multi Processors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の共有メモリの制御システムのブロック
図、第２図は第１図のメモリ制御回路部−−の回路図で
ある。
符号の説明、１・・・・・・共有メモリ、２，４・・・
・・・セレクタ、８，９・・・・・・ＣＰＵ、 １０
． １１・・・・・・デー、タバツファ、１２，１３・
・・・・・Ｃ３信号、１４・・・・・・メモ′り制御回
路、１５，１６・・・・・・メモリアクセル許可信号、
２１・・・・・−ＲＳフリップフロップ、２４゛・・・
・・・ＤＴＡＣＫ信号、２７・・・・・−ＷＡＩＴ信号
。FIG. 1 is a block diagram of a shared memory control system of the present invention, and FIG. 2 is a circuit diagram of the memory control circuit section of FIG. 1. Explanation of codes, 1... Shared memory, 2, 4...
...Selector, 8,9...CPU, 10
．． 11... Day, Tabatufa, 12, 13.
... C3 signal, 14 ... Memory control circuit, 15, 16 ... Memory accelerator permission signal,
21...-RS flip-flop, 24゛...
...DTACK signal, 27...-WAIT signal.
Claims (1)
各中央処理装置が共通にアクセスできるためのアドレス
信号、データ信号及び制御信号の切換デートを有する情
報処理装置においで、複数の中央処理装置からの前記記
憶装置のセレクト信号と、前記記憶装置のデバイスセレ
クト信号の間にＲ３７９７１７０７７回路を設けたこと
を特徴とする共有メモリの制御装置。In an information processing device that has two central processing units, a storage device, and switching dates for address signals, data signals, and control signals so that each central processing unit can commonly access the storage device, A control device for a shared memory, characterized in that an R379717077 circuit is provided between a select signal for the storage device from a processing device and a device select signal for the storage device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP527484U JPS60123051U (en) | 1984-01-20 | 1984-01-20 | shared memory controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP527484U JPS60123051U (en) | 1984-01-20 | 1984-01-20 | shared memory controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60123051U true JPS60123051U (en) | 1985-08-19 |
Family
ID=30481627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP527484U Pending JPS60123051U (en) | 1984-01-20 | 1984-01-20 | shared memory controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60123051U (en) |
-
1984
- 1984-01-20 JP JP527484U patent/JPS60123051U/en active Pending
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