JPS62147041U - - Google Patents
Info
- Publication number
- JPS62147041U JPS62147041U JP1903887U JP1903887U JPS62147041U JP S62147041 U JPS62147041 U JP S62147041U JP 1903887 U JP1903887 U JP 1903887U JP 1903887 U JP1903887 U JP 1903887U JP S62147041 U JPS62147041 U JP S62147041U
- Authority
- JP
- Japan
- Prior art keywords
- error
- unit
- circuit
- flop
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は従来のエラー・チエツク方式の１例を
示す図、第２図は本考案の１実施例のブロツク図
である。
１１ないし１５…レジスタ、２１ないし２５…
エラー・チエツク回路、３１ないし３３…エラー
保持フリツプ・フロツプ、４１ないし４ｎ…ＡＮ
Ｄゲート、５…ＯＲゲート、６…エラー制御フリ
ツプ・フロツプ、Ａ１ないしＡｎ…エラー・チエ
ツク単位、Ｔ１ないしＴｎ…エラー・チエツク単
位毎に異なる固有のタイミング信号。
FIG. 1 is a diagram showing an example of a conventional error check system, and FIG. 2 is a block diagram of an embodiment of the present invention. 11 to 15...Register, 21 to 25...
Error check circuit, 31 to 33...Error holding flip-flop, 41 to 4n...AN
D gate, 5...OR gate, 6...Error control flip-flop, A1 to An...error check unit, T1 to Tn...specific timing signal different for each error check unit.
Claims (1)
る複数の単位回路を有し、単位回路が他の単位回
路と関連を有する電子装置において、単位回路の
エラーを検出するエラー・チエツク回路と、エラ
ー・チエツク単位毎に異なつた固有のタイミング
信号に同期してエラー・チエツク回路の出力を通
すゲート手段と、上記固有のタイミング信号に同
期してゲート手段の出力をラツチするエラー保持
フリツプ・フロツプとを各単位回路毎に設け、各
単位回路のゲート手段の出力をＯＲゲートを介し
てエラー制御フリツプ・フロツプに供給し、且つ
上記エラー制御フリツプ・フロツプの状態値がオ
ンになつたとき、上記各エラー保持フリツプ・フ
ロツプが対応するエラー・チエツク回路の出力す
るエラー信号をラツチしないように構成したこと
を特徴とするエラー・チエツク装置。 An error check circuit for detecting an error in a unit circuit in an electronic device having a plurality of unit circuits constituted by gates and flip-flops, and in which each unit circuit is related to other unit circuits. Each unit includes gate means for passing the output of the error check circuit in synchronization with a unique timing signal that differs from unit to unit, and an error holding flip-flop that latches the output of the gate means in synchronization with the above-mentioned unique timing signal. Provided for each circuit, the output of the gate means of each unit circuit is supplied to an error control flip-flop via an OR gate, and when the state value of the error control flip-flop is turned on, each of the error holding flip-flops is - An error check device characterized in that the flop is configured so that the error signal output from the corresponding error check circuit is not latched.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1903887U JPS6324503Y2 (en) | 1987-02-12 | 1987-02-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1903887U JPS6324503Y2 (en) | 1987-02-12 | 1987-02-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62147041U true JPS62147041U (en) | 1987-09-17 |
| JPS6324503Y2 JPS6324503Y2 (en) | 1988-07-05 |
Family
ID=30813272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1903887U Expired JPS6324503Y2 (en) | 1987-02-12 | 1987-02-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6324503Y2 (en) |
-
1987
- 1987-02-12 JP JP1903887U patent/JPS6324503Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6324503Y2 (en) | 1988-07-05 |
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