JPS63126944U - - Google Patents
Info
- Publication number
- JPS63126944U JPS63126944U JP1570087U JP1570087U JPS63126944U JP S63126944 U JPS63126944 U JP S63126944U JP 1570087 U JP1570087 U JP 1570087U JP 1570087 U JP1570087 U JP 1570087U JP S63126944 U JPS63126944 U JP S63126944U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- bus
- request
- bus usage
- sampling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 1
Landscapes
- Multi Processors (AREA)
- Bus Control (AREA)
Description
第１図は本考案に係るバス調停回路の一実施例
を示す回路図、第２図は従来のバス調停回路の一
実施例を示す回路図、第３図は第１図図示回路図
の動作を説明するためのタイミングチヤート、第
４図は第２図図示回路図の動作を説明するための
タイミングチヤートである。
１…フリツプフロツプ、２…ゲート回路、３…
フリツプフロツプ、４…ゲート回路、５…保持回
路、６…検知回路。
FIG. 1 is a circuit diagram showing an embodiment of a bus arbitration circuit according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of a conventional bus arbitration circuit, and FIG. 3 is an operation of the circuit diagram shown in FIG. 1. FIG. 4 is a timing chart for explaining the operation of the circuit diagram shown in FIG. 2. 1...Flip-flop, 2...Gate circuit, 3...
Flip-flop, 4...gate circuit, 5...holding circuit, 6...detection circuit.
Claims (1)
を基準クロツクに同期してサンプリングする回路
と、該サンプリングする回路からの出力を優先順
位に従い選択するための回路と、該回路により選
択された信号を上記バス使用権の要求が終わるま
での期間保持すると共に、その期間が終了した時
にバス使用許可信号を出力する回路とを備えたバ
ス調停回路において、特に高速性が要求されるバ
ス使用権要求信号の状態を、他のバス使用権要求
信号とは別個に検知する回路を設けた事を特徴と
するバス調停回路。 a circuit for sampling the states of multiple signals for requesting bus usage rights in synchronization with a reference clock; a circuit for selecting outputs from the sampling circuit according to priority; In a bus arbitration circuit that is equipped with a circuit that holds a signal for a period until the request for the bus usage right ends and outputs a bus usage permission signal when the period ends, the bus usage right that requires particularly high speed. A bus arbitration circuit comprising a circuit that detects the state of a request signal separately from other bus right request signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1570087U JPS63126944U (en) | 1987-02-05 | 1987-02-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1570087U JPS63126944U (en) | 1987-02-05 | 1987-02-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63126944U true JPS63126944U (en) | 1988-08-19 |
Family
ID=30806875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1570087U Pending JPS63126944U (en) | 1987-02-05 | 1987-02-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63126944U (en) |
-
1987
- 1987-02-05 JP JP1570087U patent/JPS63126944U/ja active Pending
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