JPS63168551U

JPS63168551U -

Info

Publication number: JPS63168551U
Application number: JP5950587U
Authority: JP
Priority date: 1987-04-20
Filing date: 1987-04-20
Publication date: 1988-11-02

Description

[Brief explanation of the drawing]

第１図及び第３図は本考案の夫々異なつた実施
例を示す図、第２図は本考案のフローチヤート実
施例、第４図は従来例を示す回路図、第５図はシ
ステムが異常となるタイミングチヤートである。図において、１０はラツチ素子、２０はプライ
オリテイー付エンコーダ、３０，３１は３ステー
ト付バツフア、４０はフリツプフロツプ、５０は
オア素子、６０はノツト素子、６１はアンド素子
、７０は割込要因、８０は割込アクノリツヂ信号
、８１はリセツト信号、８２はステータス読出信
号、９０は割込信号、１００はデータバスである
。なお、図中同一符号は同一又は相当部分を示す
。 Figures 1 and 3 are diagrams showing different embodiments of the present invention, Figure 2 is a flowchart of the embodiment of the present invention, Figure 4 is a circuit diagram showing a conventional example, and Figure 5 is a system error. This is the timing chart. In the figure, 10 is a latch element, 20 is an encoder with priority, 30 and 31 are buffers with 3 states, 40 is a flip-flop, 50 is an OR element, 60 is a NOT element, 61 is an AND element, 70 is an interrupt factor, and 80 is a flip-flop. 81 is an interrupt acknowledge signal, 81 is a reset signal, 82 is a status read signal, 90 is an interrupt signal, and 100 is a data bus. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims

[Claims for Utility Model Registration] (1) In an interrupt circuit that receives a plurality of interrupt factors or more and outputs an interrupt vector and an interrupt signal to a microprocessor according to a predetermined priority, An interrupt circuit comprising means for a microprocessor to read out the interrupt vector also as status information. (2) The interrupt circuit according to claim 1, wherein the output of the interrupt vector is controlled by a flip-flop that can be reset by a microprocessor.