JPH01160551U - - Google Patents

Description

[Brief explanation of drawings]

Figure 1a shows a block diagram of an embodiment of the serial interface according to this invention.
FIG. 1b shows a block diagram in reception speed measurement mode, and FIG. 1c shows a block diagram in normal transfer mode. FIGS. 2 to 5 are examples of circuit descriptions of each part of FIG. 1a. FIG. 6 is a timing diagram of an example of serial transfer according to this invention, FIG. 7 is a block diagram of a conventional serial interface, and FIG. 8 is a timing diagram of conventional normal transfer. In the figure, 1 is a clock source selection circuit, 2 is a baud rate generator, 3 is an overflow detector, 4a and 4b are n frequency divider circuits, 5 is a reception control circuit,
6 is a transmission control circuit, 7 is a reception register, 8 is a transmission register, 9 is a reception buffer register, 10 is a transmission buffer register, 11 is a data bus, 13 is a baud rate register, 14 is a clock source selection register, 15 is a mode register, 20a, 20b,
20c and 20d are relays, and 21 is a 2 frequency divider. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Amendment July 15, 1983 The scope of claims for utility model registration is amended as follows.

[Claims for Utility Model Registration] A serial interface having a function of automatically generating the most suitable transfer clock according to the transfer speed of the IC to be transferred in serial transfer.

Claims (1)

[Scope of utility model registration request] A serial interface equipped with a function that automatically generates the most suitable transfer clock according to the transfer speed of the target IC for serial transfer.