JPS5950146U - data receiving circuit - Google Patents
data receiving circuitInfo
- Publication number
- JPS5950146U JPS5950146U JP14646482U JP14646482U JPS5950146U JP S5950146 U JPS5950146 U JP S5950146U JP 14646482 U JP14646482 U JP 14646482U JP 14646482 U JP14646482 U JP 14646482U JP S5950146 U JPS5950146 U JP S5950146U
- Authority
- JP
- Japan
- Prior art keywords
- data
- receiving circuit
- data receiving
- selection circuit
- information transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Small-Scale Networks (AREA)
- Communication Control (AREA)
- Dc Digital Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はデータ受信回路の従来例を示す図、第２図は本
考案による実施例のデータ受信回路を示す図である。
図中、４，５はデー タ送信部、６はデータ選択回路、
７はデータ受信部、１４はデータ選択信号、１５〜１７
はクロック、１８はクロック選択回路である。FIG. 1 is a diagram showing a conventional example of a data receiving circuit, and FIG. 2 is a diagram showing a data receiving circuit according to an embodiment of the present invention. In the figure, 4 and 5 are data transmitting units, 6 is a data selection circuit,
7 is a data receiving section, 14 is a data selection signal, 15 to 17
18 is a clock, and 18 is a clock selection circuit.
Claims (1)
択信号にもとづいて選択するデータ選択回路と、該デー
タ選択回路により選択されたデータを保持するラッチま
たはフリップフロップを含むデータ受信回路において、
複数の情報送信源毎にまたは情報送信源グループ毎に、
それぞれ異なる位相を有するクロックを用意するととも
に、該クロックを選択するクロック選択回路をもうけ、
上記データ選択信号にもとづいて該クロック撫択回路を
制御することにより、上記複数の情報送信源毎にまたは
情報送信源グループ毎に、その送出データを異なるクロ
ックで上記ラッチまたはフリップフロップに保持するよ
う構成したことを特徴とするデータ受信回路。In a data receiving circuit including a data selection circuit that selects data sent from a plurality of information transmission sources based on a data selection signal, and a latch or flip-flop that holds data selected by the data selection circuit,
For each information source or group of information sources,
In addition to preparing clocks each having a different phase, a clock selection circuit for selecting the clocks is provided,
By controlling the clock selection circuit based on the data selection signal, the transmitted data is held in the latch or flip-flop at a different clock for each of the plurality of information transmission sources or for each information transmission source group. A data receiving circuit characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14646482U JPS5950146U (en) | 1982-09-28 | 1982-09-28 | data receiving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14646482U JPS5950146U (en) | 1982-09-28 | 1982-09-28 | data receiving circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5950146U true JPS5950146U (en) | 1984-04-03 |
Family
ID=30326002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14646482U Pending JPS5950146U (en) | 1982-09-28 | 1982-09-28 | data receiving circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5950146U (en) |
-
1982
- 1982-09-28 JP JP14646482U patent/JPS5950146U/en active Pending
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