JPS6392485U - - Google Patents
Info
- Publication number
- JPS6392485U JPS6392485U JP18638386U JP18638386U JPS6392485U JP S6392485 U JPS6392485 U JP S6392485U JP 18638386 U JP18638386 U JP 18638386U JP 18638386 U JP18638386 U JP 18638386U JP S6392485 U JPS6392485 U JP S6392485U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- delay
- signal
- generates
- axis error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 230000010355 oscillation Effects 0.000 claims description 3
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000003708 edge detection Methods 0.000 description 1
Landscapes
- Television Signal Processing For Recording (AREA)
Description
第１図は本考案の時間軸誤差補正装置のブロツ
ク図、第２図はその検出回路の回路図、第３図は
そのタイミングチヤート、第４図は従来の時間軸
誤差検出動作のタイミングチヤートである。
１，２……遅延回路、３……電圧制御発振回路
、４……色位相補正回路、５……同期分離回路、
６……比較回路、７，８……発生回路、９……ル
ープスイツチ、１０……イコライザ回路、１１…
…検出回路、２１，２２……同期分離回路、２３
，２４，２５……モノマルチバイブレータ、２６
……ナンドゲート、２７……エツジ検出回路、２
８……判定回路。
Fig. 1 is a block diagram of the time axis error correction device of the present invention, Fig. 2 is a circuit diagram of its detection circuit, Fig. 3 is its timing chart, and Fig. 4 is a timing chart of the conventional time axis error detection operation. be. 1, 2... Delay circuit, 3... Voltage controlled oscillation circuit, 4... Color phase correction circuit, 5... Synchronization separation circuit,
6... Comparison circuit, 7, 8... Generation circuit, 9... Loop switch, 10... Equalizer circuit, 11...
...Detection circuit, 21, 22...Synchronization separation circuit, 23
, 24, 25... Mono multivibrator, 26
...Nand gate, 27...Edge detection circuit, 2
8...Judgment circuit.
Claims (1)
号を発生する発生回路と、該基準信号と該遅延回
路より出力された信号とを比較し、時間軸誤差信
号を生成する比較回路と、該時間軸誤差信号に対
応して該遅延回路の遅延を制御するクロツクを発
生する電圧制御発振回路と、該遅延回路の遅延量
を検出する検出回路と、該検出回路の出力に対応
して該時間軸誤差信号の該電圧制御発振回路への
供給を制御するスイツチとを備えることを特徴と
する時間軸誤差補正装置。 a delay circuit that delays an input signal; a generation circuit that generates a predetermined reference signal; a comparison circuit that compares the reference signal with the signal output from the delay circuit and generates a time axis error signal; a voltage controlled oscillation circuit that generates a clock that controls the delay of the delay circuit in response to an axis error signal; a detection circuit that detects the amount of delay of the delay circuit; A time axis error correction device comprising: a switch that controls supply of an error signal to the voltage controlled oscillation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18638386U JPS6392485U (en) | 1986-12-03 | 1986-12-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18638386U JPS6392485U (en) | 1986-12-03 | 1986-12-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6392485U true JPS6392485U (en) | 1988-06-15 |
Family
ID=31135892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18638386U Pending JPS6392485U (en) | 1986-12-03 | 1986-12-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6392485U (en) |
-
1986
- 1986-12-03 JP JP18638386U patent/JPS6392485U/ja active Pending
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