JPS6391860U - - Google Patents
Info
- Publication number
- JPS6391860U JPS6391860U JP18638286U JP18638286U JPS6391860U JP S6391860 U JPS6391860 U JP S6391860U JP 18638286 U JP18638286 U JP 18638286U JP 18638286 U JP18638286 U JP 18638286U JP S6391860 U JPS6391860 U JP S6391860U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- axis error
- signal
- generates
- error signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 230000010355 oscillation Effects 0.000 claims description 3
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000009499 grossing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Description
第１図は本考案の時間軸誤差補正装置のブロツ
ク図、第２図はその検出回路の回路図、第３図は
従来の時間軸誤差検出動作のタイミングチヤート
である。
１，２……遅延回路、３……電圧制御発振回路
、４……色位相補正回路、５……同期分離回路、
６……比較回路、７，８……発生回路、９……ル
ープスイツチ、１０……イコライザ回路、１１…
…検出回路、２１，２２……整流平滑回路、２３
，２４……比較回路、２５……タイマ回路、２６
……スイツチング回路、７１，７２……演算増幅
器、７３……トランジスタ。
FIG. 1 is a block diagram of the time base error correction device of the present invention, FIG. 2 is a circuit diagram of its detection circuit, and FIG. 3 is a timing chart of a conventional time base error detection operation. 1, 2... Delay circuit, 3... Voltage controlled oscillation circuit, 4... Color phase correction circuit, 5... Synchronization separation circuit,
6... Comparison circuit, 7, 8... Generation circuit, 9... Loop switch, 10... Equalizer circuit, 11...
...detection circuit, 21, 22... rectification smoothing circuit, 23
, 24... Comparison circuit, 25... Timer circuit, 26
... Switching circuit, 71, 72 ... Operational amplifier, 73 ... Transistor.
Claims (1)
号を発生する発生回路と、該基準信号と該遅延回
路より出力された信号とを比較し、時間軸誤差信
号を生成する比較回路と、該時間軸誤差信号に対
応して該遅延回路の遅延を制御するクロツクを発
生する電圧制御発振回路と、該時間軸誤差信号の
レベルを検出する検出回路と、該検出回路の出力
に対応して該時間軸誤差信号の該電圧制御発振回
路への供給を制御するスイツチとを備えることを
特徴とする時間軸誤差補正装置。 a delay circuit that delays an input signal; a generation circuit that generates a predetermined reference signal; a comparison circuit that compares the reference signal with the signal output from the delay circuit and generates a time axis error signal; a voltage controlled oscillation circuit that generates a clock that controls the delay of the delay circuit in response to the axis error signal; a detection circuit that detects the level of the time axis error signal; A time axis error correction device comprising: a switch that controls supply of an axis error signal to the voltage controlled oscillation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18638286U JPS6391860U (en) | 1986-12-03 | 1986-12-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18638286U JPS6391860U (en) | 1986-12-03 | 1986-12-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6391860U true JPS6391860U (en) | 1988-06-14 |
Family
ID=31135890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18638286U Pending JPS6391860U (en) | 1986-12-03 | 1986-12-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6391860U (en) |
-
1986
- 1986-12-03 JP JP18638286U patent/JPS6391860U/ja active Pending