JPS6448933U - - Google Patents
Info
- Publication number
- JPS6448933U JPS6448933U JP14345487U JP14345487U JPS6448933U JP S6448933 U JPS6448933 U JP S6448933U JP 14345487 U JP14345487 U JP 14345487U JP 14345487 U JP14345487 U JP 14345487U JP S6448933 U JPS6448933 U JP S6448933U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- reference signal
- external reference
- pulse signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案の一実施例を示す図、第２図は
その各部波形図、第３図は従来例を示す図である
。
１……入力端子、４……位相比較回路、５……
フイルタ回路、６……電圧制御発振回路、７……
分周回路、８……信号出力端子、９……反転検出
回路、１０……切換回路、１１……パルス信号発
生回路。
FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram of each part thereof, and FIG. 3 is a diagram showing a conventional example. 1...Input terminal, 4...Phase comparison circuit, 5...
Filter circuit, 6... Voltage controlled oscillation circuit, 7...
Frequency dividing circuit, 8... Signal output terminal, 9... Inversion detection circuit, 10... Switching circuit, 11... Pulse signal generation circuit.
Claims (1)
エラー信号を制御電圧に変換するフイルタ回路と
、このフイルタ回路からの制御電圧に応じて発振
周波数が制御される電圧制御発振回路と、この電
圧制御発振回路からの出力信号と外部基準信号と
を入力信号とし、この入力信号の内、いずれか一
つを選択的に位相比較回路へ基準信号として供給
する切換回路と、前記外部基準信号の反転に応じ
て所定幅のパルス信号を前記切換回路へ切換制御
信号として供給するパルス信号発生回路とを備え
、前記外部基準信号の非反転時、前記外部基準信
号に代えて前記電圧制御発振回路の発振出力信号
を基準信号として前記位相比較回路に供給するよ
うにしたことを特徴とするＰＬＬ回路。 (2) パルス信号発生回路より発生されるパルス
信号の幅が、外部基準信号のビツト間隔よりも少
許長く設定されていることを特徴とする実用新案
登録請求の範囲第１項記載のＰＬＬ回路。[Claims for Utility Model Registration] (1) A phase comparison circuit, a filter circuit that converts an error signal from the phase comparison circuit into a control voltage, and an oscillation frequency that is controlled according to the control voltage from the filter circuit. A voltage controlled oscillator circuit, and a switching circuit that takes an output signal from the voltage controlled oscillator circuit and an external reference signal as input signals, and selectively supplies one of the input signals to the phase comparator circuit as a reference signal. and a pulse signal generation circuit for supplying a pulse signal of a predetermined width to the switching circuit as a switching control signal in response to inversion of the external reference signal, and a pulse signal generating circuit that supplies a pulse signal of a predetermined width to the switching circuit as a switching control signal in response to inversion of the external reference signal, and when the external reference signal is not inverted, the pulse signal generation circuit is configured to replace the external reference signal. The PLL circuit is characterized in that the oscillation output signal of the voltage controlled oscillation circuit is supplied to the phase comparator circuit as a reference signal. (2) The PLL circuit according to claim 1, wherein the width of the pulse signal generated by the pulse signal generating circuit is set to be slightly longer than the bit interval of the external reference signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14345487U JPS6448933U (en) | 1987-09-18 | 1987-09-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14345487U JPS6448933U (en) | 1987-09-18 | 1987-09-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6448933U true JPS6448933U (en) | 1989-03-27 |
Family
ID=31410296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14345487U Pending JPS6448933U (en) | 1987-09-18 | 1987-09-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6448933U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5648726A (en) * | 1979-09-28 | 1981-05-02 | Hitachi Ltd | Phase locked loop circuit |
-
1987
- 1987-09-18 JP JP14345487U patent/JPS6448933U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5648726A (en) * | 1979-09-28 | 1981-05-02 | Hitachi Ltd | Phase locked loop circuit |
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