JPS62114578U - - Google Patents

Info

Publication number
JPS62114578U
JPS62114578U JP190486U JP190486U JPS62114578U JP S62114578 U JPS62114578 U JP S62114578U JP 190486 U JP190486 U JP 190486U JP 190486 U JP190486 U JP 190486U JP S62114578 U JPS62114578 U JP S62114578U
Authority
JP
Japan
Prior art keywords
circuit
synchronization signal
output
delay
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP190486U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP190486U priority Critical patent/JPS62114578U/ja
Publication of JPS62114578U publication Critical patent/JPS62114578U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Television Signal Processing For Recording (AREA)
  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の時間軸誤差補正装置のブロツ
ク図、第2図はそのジツタに着目した等価ブロツ
ク図、第3図は従来の時間軸誤差補正装置のブロ
ツク図、第4図はそのジツタに着目した等価ブロ
ツク図である。 1,2……遅延回路、3,8……同期分離回路
、4,9……比較回路、5,10……基準信号発
生回路、6,11……イコライザ増幅回路、7,
12……電圧制御発振器、21……増幅回路、2
2,23……加算回路。
Fig. 1 is a block diagram of the time axis error correction device of the present invention, Fig. 2 is an equivalent block diagram focusing on the jitter, Fig. 3 is a block diagram of a conventional time axis error correction device, and Fig. 4 is the jitter. FIG. 2 is an equivalent block diagram focusing on 1, 2... Delay circuit, 3, 8... Synchronization separation circuit, 4, 9... Comparison circuit, 5, 10... Reference signal generation circuit, 6, 11... Equalizer amplifier circuit, 7,
12... Voltage controlled oscillator, 21... Amplification circuit, 2
2, 23...Addition circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力される信号を遅延する遅延回路と、該遅延
回路の遅延量を制御する制御回路と、該遅延回路
の出力から第1の同期信号を分離する第1の同期
分離回路と、分離された該第1の同期信号と第1
の基準同期信号との位相を比較し、位相差を出力
する第1の比較回路と、該遅延回路の出力から第
2の同期信号を分離する第2の同期分離回路と、
分離された該第2の同期信号と第2の基準同期信
号との位相を比較し、位相差を出力する第2の比
較回路と、該第2の比較回路の出力のレベルを制
御するレベル制御回路と、該第1の比較回路の出
力と該レベル制御回路の出力とを加算して該制御
回路に出力する加算回路とを有することを特徴と
する時間軸誤差補正装置。
a delay circuit that delays an input signal; a control circuit that controls the amount of delay of the delay circuit; a first synchronization separation circuit that separates a first synchronization signal from the output of the delay circuit; the first synchronization signal and the first
a first comparison circuit that compares the phase with a reference synchronization signal and outputs a phase difference; a second synchronization separation circuit that separates a second synchronization signal from the output of the delay circuit;
a second comparison circuit that compares the phases of the separated second synchronization signal and a second reference synchronization signal and outputs a phase difference; and a level control that controls the level of the output of the second comparison circuit. A time-base error correction device comprising: a circuit; and an addition circuit that adds the output of the first comparison circuit and the output of the level control circuit and outputs the result to the control circuit.
JP190486U 1986-01-10 1986-01-10 Pending JPS62114578U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP190486U JPS62114578U (en) 1986-01-10 1986-01-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP190486U JPS62114578U (en) 1986-01-10 1986-01-10

Publications (1)

Publication Number Publication Date
JPS62114578U true JPS62114578U (en) 1987-07-21

Family

ID=30780247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP190486U Pending JPS62114578U (en) 1986-01-10 1986-01-10

Country Status (1)

Country Link
JP (1) JPS62114578U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5767383A (en) * 1980-10-14 1982-04-23 Mitsubishi Electric Corp Jitter correction device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5767383A (en) * 1980-10-14 1982-04-23 Mitsubishi Electric Corp Jitter correction device

Similar Documents

Publication Publication Date Title
JPS62114578U (en)
JPH03120127U (en)
JPS62203530U (en)
JPS6390381U (en)
JPS6381480U (en)
JPS63114505U (en)
JPS6372936U (en)
JPS6391860U (en)
JPH01133873U (en)
JPH0170481U (en)
JPS6392485U (en)
JPH0375683U (en)
JPS6226978U (en)
JPS611978U (en) Timing signal generation circuit
JPH0295988U (en)
JPS6415428U (en)
JPS62186533U (en)
JPS6284277U (en)
JPS6440913U (en)
JPS6411033U (en)
JPS61121100U (en)
JPS633644U (en)
JPH0238881U (en)
JPS588240U (en) phase synchronized circuit
JPH02134788U (en)