JPH0295988U - - Google Patents
Info
- Publication number
- JPH0295988U JPH0295988U JP491089U JP491089U JPH0295988U JP H0295988 U JPH0295988 U JP H0295988U JP 491089 U JP491089 U JP 491089U JP 491089 U JP491089 U JP 491089U JP H0295988 U JPH0295988 U JP H0295988U
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- frequency
- circuit
- amplitude
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 15
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000012937 correction Methods 0.000 description 1
Landscapes
- Video Image Reproduction Devices For Color Tv Systems (AREA)
- Details Of Television Scanning (AREA)
Description
第１図は本考案回路の一実施例の要部概略図、
第２図はダイナミツクコンバーゼンス回路の概略
構成図、第３図は従来のダイナミツクコンバーゼ
ンス回路の要部概略図である。
１……基本波形発生回路、１１……垂直鋸波発
生回路、１２……水平鋸波発生回路、１３……垂
直パラボラ波発生回路、１４……水平パラボラ波
発生回路１４、２……各種補正波形発生回路、３
……可変抵抗部、４……バツフア回路４、５……
出力回路、６……定電流源、７，７′……積分回
路、Ｃ１……コンデンサ（第１のコンデンサ）、
Ｃ４……コンデンサ（第１の補助コンデンサ）、
Ｃ３……コンデンサ（第２のコンデンサ）、Ｃ５
……コンデンサ（第２の補助コンデンサ）、Ｃ２
……コンデンサ、ＶＲ１……可変抵抗（鋸波振幅
調整手段）、ＶＲ２……可変抵抗（パラボラ波振
幅調整手段）、Ｑ１……トランジスタ、Ａ１……
バツフア、Ａ２……ＯＰアンプ、Ｓ１，Ｓ２，Ｓ
３，Ｓ４，Ｓ５，Ｓ６，Ｓ７……スイツチ。
FIG. 1 is a schematic diagram of the main parts of an embodiment of the circuit of the present invention;
FIG. 2 is a schematic diagram of a dynamic convergence circuit, and FIG. 3 is a schematic diagram of the main parts of a conventional dynamic convergence circuit. 1... Basic waveform generation circuit, 11... Vertical sawtooth wave generation circuit, 12... Horizontal sawtooth wave generation circuit, 13... Vertical parabolic wave generation circuit, 14... Horizontal parabolic wave generation circuit 14, 2... Various corrections Waveform generation circuit, 3
...Variable resistance section, 4...Buffer circuits 4, 5...
Output circuit, 6...constant current source, 7,7'...integrator circuit, C1 ...capacitor (first capacitor),
C 4 ... Capacitor (first auxiliary capacitor),
C 3 ... Capacitor (second capacitor), C 5
... Capacitor (second auxiliary capacitor), C 2
... Capacitor, VR 1 ... Variable resistor (sawtooth amplitude adjustment means), VR 2 ... Variable resistance (parabolic wave amplitude adjustment means), Q 1 ... Transistor, A 1 ...
Buffer, A 2 ... OP amplifier, S 1 , S 2 , S
3 , S 4 , S 5 , S 6 , S 7 ... switch.
Claims (1)
し、同期パルスに同期して前記第１のコンデンサ
から放電させて鋸波を形成し、抵抗と第２のコン
デンサを備える積分回路により、形成した鋸波を
積分してパラボラ波を形成する手段を具備するダ
イナミツクコンバーゼンス回路において、 入力される同期パルスの周波数に応じて選択的
に前記第１のコンデンサと並列に接続される第１
の補助コンデンサと、入力される同期パルスの周
波数に応じて選択的に前記第２のコンデンサと並
列に接続される第２の補助コンデンサと、形成さ
れる鋸波の振幅を入力される同期パルスの周波数
に対応して一定の値に調整する鋸波振幅調整手段
と、形成されるパラボラ波の振幅を入力される同
期パルスの周波数に対応して一定の値に調整する
パラボラ波振幅調整手段とを備える事を特徴とす
るダイナミツクコンバーゼンス回路。[Claims for Utility Model Registration] A first capacitor is charged with a current from a constant current source, the first capacitor is discharged in synchronization with a synchronous pulse to form a sawtooth wave, and a resistor and a second capacitor are charged. In a dynamic convergence circuit comprising a means for integrating a sawtooth wave formed by an integrating circuit to form a parabolic wave, an integral circuit is selectively connected in parallel with the first capacitor according to the frequency of an input synchronizing pulse. 1st connected
a second auxiliary capacitor selectively connected in parallel with the second capacitor according to the frequency of the input synchronization pulse; sawtooth wave amplitude adjusting means for adjusting the amplitude to a constant value in accordance with the frequency; and parabolic wave amplitude adjusting means for adjusting the amplitude of the formed parabolic wave to a constant value in accordance with the frequency of the input synchronization pulse. A dynamic convergence circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP491089U JPH079491Y2 (en) | 1989-01-18 | 1989-01-18 | Dynamic convergence circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP491089U JPH079491Y2 (en) | 1989-01-18 | 1989-01-18 | Dynamic convergence circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0295988U true JPH0295988U (en) | 1990-07-31 |
| JPH079491Y2 JPH079491Y2 (en) | 1995-03-06 |
Family
ID=31207837
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP491089U Expired - Lifetime JPH079491Y2 (en) | 1989-01-18 | 1989-01-18 | Dynamic convergence circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH079491Y2 (en) |
-
1989
- 1989-01-18 JP JP491089U patent/JPH079491Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH079491Y2 (en) | 1995-03-06 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |