JPH0410431U - - Google Patents
Info
- Publication number
- JPH0410431U JPH0410431U JP1990050923U JP5092390U JPH0410431U JP H0410431 U JPH0410431 U JP H0410431U JP 1990050923 U JP1990050923 U JP 1990050923U JP 5092390 U JP5092390 U JP 5092390U JP H0410431 U JPH0410431 U JP H0410431U
- Authority
- JP
- Japan
- Prior art keywords
- amplitude
- digital signal
- delay
- delay stage
- cmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006835 compression Effects 0.000 claims 2
- 238000007906 compression Methods 0.000 claims 2
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Pulse Circuits (AREA)
Description
第１図は、この考案の可変遅延回路の一例を示
す接続図、第２図は、その各部に得られるデジタ
ル信号の態様を示す図、第３図および第４図は、
それぞれ、この考案の可変遅延回路の他の例を示
す接続図、第５図は、従来のタツプ付き遅延ライ
ンの一例を示す接続図、第６図は、従来の可変容
量ダイオードを用いた遅延回路の一例を示す接続
図である。
FIG. 1 is a connection diagram showing an example of the variable delay circuit of this invention, FIG. 2 is a diagram showing the form of digital signals obtained in each part of the circuit, and FIGS. 3 and 4 are:
5 is a connection diagram showing another example of the variable delay circuit of this invention, FIG. 5 is a connection diagram showing an example of a conventional tapped delay line, and FIG. 6 is a connection diagram showing a conventional delay circuit using a variable capacitance diode. It is a connection diagram showing an example.
Claims (1)
振幅圧縮部と、 ＣＭＯＳ・ＩＣによつて構成され、上記振幅圧
縮部の出力デジタル信号を遅延させる遅延段と、 上記ＣＭＯＳ・ＩＣに対する電源電圧を調整す
ることによつて上記遅延段における遅延時間を設
定する調整設定部と、 上記遅延段の出力デジタル信号の振幅を上記所
定振幅に伸長する振幅伸長部と、 を備える可変遅延回路。[Claims for Utility Model Registration] An amplitude compression unit that compresses the amplitude of an input digital signal having a predetermined amplitude; a delay stage that is configured by a CMOS IC and delays the output digital signal of the amplitude compression unit; and the CMOS - A variable device comprising: an adjustment setting section that sets the delay time in the delay stage by adjusting the power supply voltage to the IC; and an amplitude extension section that extends the amplitude of the output digital signal of the delay stage to the predetermined amplitude. delay circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990050923U JPH0410431U (en) | 1990-05-16 | 1990-05-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990050923U JPH0410431U (en) | 1990-05-16 | 1990-05-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0410431U true JPH0410431U (en) | 1992-01-29 |
Family
ID=31569896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990050923U Pending JPH0410431U (en) | 1990-05-16 | 1990-05-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0410431U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006139519A (en) * | 2004-11-11 | 2006-06-01 | Advantest Corp | Power supply circuit and testing device |
-
1990
- 1990-05-16 JP JP1990050923U patent/JPH0410431U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006139519A (en) * | 2004-11-11 | 2006-06-01 | Advantest Corp | Power supply circuit and testing device |
| JP4549160B2 (en) * | 2004-11-11 | 2010-09-22 | 株式会社アドバンテスト | Test equipment |
| KR101218910B1 (en) * | 2004-11-11 | 2013-01-07 | 주식회사 아도반테스토 | Power supply circuit and test device |
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