JPH01117115U - - Google Patents

Info

Publication number
JPH01117115U
JPH01117115U JP1124288U JP1124288U JPH01117115U JP H01117115 U JPH01117115 U JP H01117115U JP 1124288 U JP1124288 U JP 1124288U JP 1124288 U JP1124288 U JP 1124288U JP H01117115 U JPH01117115 U JP H01117115U
Authority
JP
Japan
Prior art keywords
processing circuit
external
filter
signal
external processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1124288U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1124288U priority Critical patent/JPH01117115U/ja
Publication of JPH01117115U publication Critical patent/JPH01117115U/ja
Pending legal-status Critical Current

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  • Dc Digital Transmission (AREA)
  • Noise Elimination (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す構成図、第2
図は従来例を示す図である。 1…高周波ノイズフイルタ、2…デイジタルフ
イルタ、3…デイジタル入力信号、4…低周波ノ
イズフイルタ、5…デイジタル出力信号、6…マ
ルチプレクサ、7…出力端子、8…入力端子、9
…セレクト信号。
Figure 1 is a configuration diagram showing one embodiment of the present invention;
The figure shows a conventional example. 1...High frequency noise filter, 2...Digital filter, 3...Digital input signal, 4...Low frequency noise filter, 5...Digital output signal, 6...Multiplexer, 7...Output terminal, 8...Input terminal, 9
...Select signal.

Claims (1)

【実用新案登録請求の範囲】 複数のデイジタル入力信号をセレクト信号の到
来の度に一定の切替周期で選択して取込むマルチ
プレクサと、 前記マルチプレクサで取込まれたデイジタル入
力信号を外部処理回路へ出力するための外部出力
端子と、 前記外部処理回路の出力信号を入力するための
外部入力端子と、 前記外部入力端子を介して入力する前記出力信
号中に混成されたノイズ成分を除去するとともに
前記マルチプレクサに対して前記セレクト信号を
供給するノイズフイルタと、 を備えることを特徴とするデイジタルフイルタ。
[Claim for Utility Model Registration] A multiplexer that selects and captures a plurality of digital input signals at a constant switching cycle each time a select signal arrives, and outputs the digital input signal captured by the multiplexer to an external processing circuit. an external output terminal for inputting the output signal of the external processing circuit; and an external input terminal for inputting the output signal of the external processing circuit; A digital filter comprising: a noise filter that supplies the selection signal to the filter.
JP1124288U 1988-02-01 1988-02-01 Pending JPH01117115U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1124288U JPH01117115U (en) 1988-02-01 1988-02-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1124288U JPH01117115U (en) 1988-02-01 1988-02-01

Publications (1)

Publication Number Publication Date
JPH01117115U true JPH01117115U (en) 1989-08-08

Family

ID=31219622

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1124288U Pending JPH01117115U (en) 1988-02-01 1988-02-01

Country Status (1)

Country Link
JP (1) JPH01117115U (en)

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