JPH0236241U - - Google Patents
Info
- Publication number
- JPH0236241U JPH0236241U JP11492188U JP11492188U JPH0236241U JP H0236241 U JPH0236241 U JP H0236241U JP 11492188 U JP11492188 U JP 11492188U JP 11492188 U JP11492188 U JP 11492188U JP H0236241 U JPH0236241 U JP H0236241U
- Authority
- JP
- Japan
- Prior art keywords
- phase difference
- delay
- circuit
- binary digital
- digital signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000000605 extraction Methods 0.000 claims description 2
- 230000003111 delayed effect Effects 0.000 claims 2
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Description
第1図は本考案の一実施例のブロツク図、第2
図は本考案の一実施例の動作を説明するためのタ
イムチヤート、第3図は従来のクロツク抽出装置
のブロツク図、第4図は第3図のクロツク装置の
動作を説明するためのタイムチヤートである。
1……入力端子、2……フイルタ、3……遅延
回路、6……出力端子、11……位相差検出回路
、12……選択回路。
Figure 1 is a block diagram of one embodiment of the present invention;
The figure is a time chart for explaining the operation of an embodiment of the present invention, FIG. 3 is a block diagram of a conventional clock extraction device, and FIG. 4 is a time chart for explaining the operation of the clock device of FIG. 3. It is. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Filter, 3... Delay circuit, 6... Output terminal, 11... Phase difference detection circuit, 12... Selection circuit.
Claims (1)
の遅延信号を作成する遅延回路と、 この遅延回路から出力される前記遅延信号と前
記2値デイジタル信号との位相差を検出する位相
差検出回路と、 この位相差検出回路による検出結果に基づき前
記複数の遅延信号から1つの遅延信号を取出して
クロツクとして出力する選択回路とを備えたこと
を特徴とするクロツク抽出装置。[Claims for Utility Model Registration] A delay circuit that delays an incoming binary digital signal to create a plurality of delayed signals, and a phase difference between the delayed signal and the binary digital signal output from the delay circuit. A clock extraction device comprising: a phase difference detection circuit for detecting a phase difference; and a selection circuit for extracting one delay signal from the plurality of delay signals and outputting it as a clock based on the detection result by the phase difference detection circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11492188U JPH0236241U (en) | 1988-09-02 | 1988-09-02 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11492188U JPH0236241U (en) | 1988-09-02 | 1988-09-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0236241U true JPH0236241U (en) | 1990-03-08 |
Family
ID=31356106
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11492188U Pending JPH0236241U (en) | 1988-09-02 | 1988-09-02 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0236241U (en) |
-
1988
- 1988-09-02 JP JP11492188U patent/JPH0236241U/ja active Pending
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