JPS61111273U - - Google Patents

Description

[Brief explanation of the drawing]

1 and 2 are block diagrams and signal waveform diagrams for explaining the operation of an embodiment of the circuit of the present invention, respectively; FIGS. 3 and 4 are diagrams showing the phase relationship between the reference signal and the color burst signal; FIG. 5 is a diagram showing the signs of the color burst signal in each state and the color burst signal one clock before, FIG. 6 is a diagram showing the relationship between the sign of the signal to be stored in the ROM and the detected output data, and FIG. and FIG. 8 are block diagrams of various examples of conventional circuits. 12...Video signal input terminal, 13...Clock input terminal, 14...4N base counter, 15...R
OM, 16...N clock delay device, 17...Color killer detection signal output terminal.

Claims (1)

[Scope of utility model registration request] Frequency fB of a color burst signal sampled at a constant sampling frequency fC and the sampling frequency fC
In a digital color killer detection circuit that performs color killer detection in a circuit that handles video signals with a relationship of fC = 4NfB (N is an integer of 1 or more), the clock of the sampling frequency fC is a frequency divider for extracting each frequency-divided output signal, a delay device for delaying the incoming color burst signal or noise component by one sampling period 1/fC, and each frequency-divided output signal of the frequency divider. , the sign of the incoming color burst signal or noise component, and the sign of the output signal of the delay device, the phase of the incoming color burst signal or noise component is divided by 4N from the frequency divider. It is a circuit that stores in advance whether or not it is within the ±90° range with respect to the output signal, and receives the sign of each of the above signals and outputs a color killer detection signal if it is not within the ±90° range. A digital color killer detection circuit.