JPS6144981U - Phase difference measuring device - Google Patents
Phase difference measuring deviceInfo
- Publication number
- JPS6144981U JPS6144981U JP12967484U JP12967484U JPS6144981U JP S6144981 U JPS6144981 U JP S6144981U JP 12967484 U JP12967484 U JP 12967484U JP 12967484 U JP12967484 U JP 12967484U JP S6144981 U JPS6144981 U JP S6144981U
- Authority
- JP
- Japan
- Prior art keywords
- phase difference
- delayed
- outputs
- measuring device
- delayed signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Measuring Phase Differences (AREA)
- Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【図面の簡単な説明】
第１図は本考案による位相差測定装置の一実施例を示す
ブロック図、第２図は第１図の各部の信号を示す信号波
形図、第３図はＤ型フリップフロツプ回路及びエクスク
ルーシブオア回路の論理動作の説明に供する略線図であ
る。
３１・・・・・・位相遅延回路、３２１〜３２Ｎ・・・
・・・Ｄ型フリツプフロップ回路、３３１・・・３３（
Ｎ−１）・・・・・・エクスクルーシブオア回路、ＳＣ
， ＳＣ２〜ＳＣＮ・・・・・・遅延信号。[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment of the phase difference measuring device according to the present invention, Fig. 2 is a signal waveform diagram showing signals of each part of Fig. 1, and Fig. 3 is a D-type FIG. 3 is a schematic diagram for explaining the logical operation of a flip-flop circuit and an exclusive OR circuit. 31... Phase delay circuit, 321-32N...
...D type flip-flop circuit, 331...33(
N-1)...Exclusive OR circuit, SC
, SC2 to SCN...Delayed signal.
Claims (1)
遅延した複数の遅延信号を出力する位相遅延回路と、カ
ラーフレーミングパルスの立上り時点又は立下り時点に
おける上記遅延信号の論理状態を検出して出力する上記
遅延信号毎に設けられた状態検出回路と、遅延量が単位
量異なる上記遅延信号を入力する２個の上記状態検出回
路の出力信号を比較する複数の状態切換点検出回路とを
具えたことを特徴とする位相差測定装置。a phase delay circuit that outputs a plurality of delayed signals having a plurality of delay steps and delaying an incoming color subcarrier pulse; and a phase delay circuit that detects and outputs the logic state of the delayed signal at the rising edge or falling edge of the color framing pulse. A state detection circuit provided for each of the delayed signals, and a plurality of state switching point detection circuits that compare the output signals of the two state detection circuits that receive the delayed signals having different delay amounts by a unit amount. A phase difference measurement device featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12967484U JPS6144981U (en) | 1984-08-27 | 1984-08-27 | Phase difference measuring device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12967484U JPS6144981U (en) | 1984-08-27 | 1984-08-27 | Phase difference measuring device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6144981U true JPS6144981U (en) | 1986-03-25 |
| JPH0349509Y2 JPH0349509Y2 (en) | 1991-10-22 |
Family
ID=30688291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12967484U Granted JPS6144981U (en) | 1984-08-27 | 1984-08-27 | Phase difference measuring device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6144981U (en) |
-
1984
- 1984-08-27 JP JP12967484U patent/JPS6144981U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0349509Y2 (en) | 1991-10-22 |
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