JPS5840960U

JPS5840960U - Stereo signal demodulation circuit

Info

Publication number: JPS5840960U
Application number: JP13664881U
Authority: JP
Inventors: 井上　秋男
Original assignee: 三洋電機株式会社
Priority date: 1981-09-14
Filing date: 1981-09-14
Publication date: 1983-03-17

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のステレオ信号復調回路のブロック結線図
、第２図ａ−〜ｊは第１図の動昂説明用タイミングチャ
ート、第３図以下の図面はこの考案のステレオ信号復調
回路の１実施例を示し、第３図はブロック結線図、第４
図ａ〜０は第３図の動作説明用タイミングチャート、第
５図は第３図の応答特性曲線図である。１・・・抽出用フィルタ、３ｂ・・・ＰＬＬ回路、１０
ｂ・・・トリガ回路、１５・・・排除回路、３０，３１
゜３２・・・第１、第２、第３半導体スイッチ、３３゜
３４．３５・・・第１、第２、第３信号保持回路、４４
・・・演算回路、ＩＮ・・・信号入力端子、０ＵＴＩ　
。０ＵＴｒ・・・左、右チヤンネル用出力端子。FIG. 1 is a block diagram of a conventional stereo signal demodulation circuit, FIG. 2 a-j is a timing chart for explaining the motion of FIG. 1, and FIG. An example is shown, FIG. 3 is a block wiring diagram, and FIG. 4 is a block diagram.
FIGS. a to 0 are timing charts for explaining the operation of FIG. 3, and FIG. 5 is a response characteristic curve diagram of FIG. 3. 1... Extraction filter, 3b... PLL circuit, 10
b...Trigger circuit, 15...Exclusion circuit, 30, 31
゜32...First, second, third semiconductor switch, 33゜34.35...First, second, third signal holding circuit, 44
...Arithmetic circuit, IN...Signal input terminal, 0UTI
. 0UTr...Output terminal for left and right channels.

Claims

[Scope of utility model registration request]

In a stereo signal demodulation circuit that outputs left and right channel signals separated by demodulation of an input FM stereo modulation signal, an extraction filter that extracts a pilot signal with an angular velocity % times the angular velocity ω of a subcarrier; A PLL circuit whose reference signal is the pilot signal from
When the output signal of is input and the phase angle of the subcarrier is 2Nw or (2N+1)w and 2N? r+? r12,
(2N+1)? r+? When r12, the first,
a trigger circuit that outputs second and third trigger signals, and first, second, and third semiconductor switches that are closed to each of the trigger signals and receive the stereo modulation signal via the pilot signal elimination circuit; circuit, first, second, and third signal holding circuits that hold the stereo modulated signal via each of the switch circuits, and the left and right channel signals are respectively controlled by calculating the output signals of the respective signal holding circuits. A stereo signal demodulation circuit comprising an output arithmetic circuit.