JPS61205023A - Glitch eliminating circuit for d/a conversion output - Google Patents

Abstract

PURPOSE:To reduce the cost of a glitch eliminating circuit by using a switched capacitor low-class filter circuit and a clock synchronizing circuit. CONSTITUTION:A D/A converting circuit 10 is connected to a switched capacitor low-class filter circuit 11 and a clock synchronizing circuit 12. At the same time, the circuit 11 is connected to the circuit 12. Then the circuit 10 receives a digital signal 20 and delivers a timing signal 21 and the 1st analog signal 22 containing the D/A converted glitch. The circuit 12 receives the signal 21 and the 1st clock signal 23 synchronous with the signal 21 and delivers the 2nd clock signal 24. Then the circuit 11 receives the signal 22 and the signal 24 and delivers the glitch of the signal 22 and the 2nd analog signal 25 with its high frequency component excluded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a glitch removal circuit for transform output.

(Prior art) For example, Eugene R, Hnatek, translated by Daijibe Kubo and Kato, ``RJl Shinn/at~Usago Converter Need Day Manual'' (April 25, 1970), as shown in P. 49 and P. 52. As shown in Figure 2, when the input digital signal changes, a very large spike called a ``1 glitch'' may occur in the output due to the operating time difference of the internal circuit. Figure 2 shows this. In this output waveform diagram, 1 is an analog waveform outputted to the conversion circuit, and 2 is a glitch that appears in the waveform.

FIG. 3 is a block diagram of a conventional technology for removing this glitch 2, in which 4 is a D/A conversion circuit, 5 is a temple hold circuit, 6 is a low-pass filter circuit, and the D/A conversion circuit 4 converts a digital signal into an analog signal. The sample and hold circuit enters a sample state and outputs the same voltage during a period when there is no glitch 2 in this output signal, and during a period when there is a glitch, it enters a hold state and maintains a flat state, and when outputting Remove glitch 2.

Further, the low-pass filter circuit 6 is for removing high frequency components in the output and outputting it to an amplifier circuit or the like.

(Problems to be Solved by the Invention) However, since the sample-and-hold circuit is expensive, there is a problem in that the price of a device using the circuit with the above-mentioned configuration is high.

(Means for solving the problem) A timing signal from a color conversion circuit and a first clock signal that is synchronized with this timing signal are input, and the conversion circuit that is to be synchronized with the timing signal is known in advance. a clock synchronization circuit that outputs a second clock signal having a period longer than twice the maximum glitch time;
A glitch removal circuit was constructed from a switched capacitor low-pass filter circuit that selectively connects the input from the D/A conversion circuit in accordance with the second clock signal.

(Operation) When the D/A conversion circuit outputs a timing signal, the clock synchronization circuit outputs a second clock signal in synchronization with this. In synchronization with this signal, the switched capacitor low-pass filter circuit disconnects the second clock signal for 1/2 of the time, so the timing signal is output from the switched capacitor low-pass filter circuit during this time. Input the output of the previous conversion circuit, apply a low-pass filter, and output it.
Remove glitches.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention. D/
The A conversion circuit IO is connected to the switched capacitor low-pass filter circuit 11 and the clock synchronization circuit 12, and the switched capacitor low-pass filter circuit 1 is connected to the clock synchronization circuit 12. Further, the D/A conversion circuit receives a digital signal 20, and outputs a first analog signal 22 that is D/A converted with a timing signal 21 and includes a glitch.

The clock synchronization circuit 12 receives the timing signal 21 and a first clock signal 23 synchronized with this signal, and sends out a second clock signal 24, which will be described in detail later.

The switched capacitor low-pass filter circuit 11 is connected to the first
The second analog signal 22 and the second clock signal 24 are received, and the second analog signal 25 from which glitches and high frequency components of the first analog signal 22 are removed is sent out.

Here, the switched low-pass filter circuit 11 is composed of a capacitor, an analog switch, and an amplifier, and performs periodic switching based on a periodic lock signal from the outside, for example, when the clock signal is in the "H" state. If so, the input terminal is not connected to anything, and if it is in the "L" state, the input terminal is connected to the internal capacitor.Hereafter, the state where the capacitor is connected is called the "sample state", and the state where it is not connected is called the "hold state". The sample state and hold state are determined by the second clock signal 24 from the clock synchronization circuit 12, and will be described in detail below.

The second clock signal 24 is synchronized with the timing signal 21 indicating the start of conversion and the first clock signal, and its 1/2 period is the time when the output of the D/A conversion due to a glitch is not within the standard error. It must be larger than the maximum value, and its phase must be such that upon receiving the timing signal 21, the motherboard low-pass filter circuit 11 can be switched to the hold state. FIG. 4 is a waveform diagram showing the relationship between the timing signal 21, the first clock signal 23, and the second clock signal 24. In the figure, the upward arrow of the timing signal 21 indicates the start of conversion, and jglttgz, etc. is the time when the output of one conversion is not within the standard error range due to a glitch. The maximum value of this time is indicated in the standards for D/A conversion circuits. When the value is tg and the period of the second clock signal 24 is T2-, in order to keep the switched low-pass filter circuit 11 in the hold state during the time tg, Tx )2 t g is applied. There must be. Further, when the period of the first clock signal 23 is TI, the second clock signal 24 is
Since the frequency of the clock signal 23 is divided, there is a relationship of Tz=nT1, where n is a natural number.

By doing this, the switched to high-pass low-pass filter circuit 11 is periodically put out of the hold state for a time T2/2, and during that time the value of the analog output 22 of the D/A conversion output circuit immediately before the hold state is maintained. The second analog signal 25 is sent to an amplifier circuit or the like by holding the signal to remove the influence of glitches and further removing high frequency components.

(Effects of the invention) As explained in detail above, the glitch removal circuit is constructed from a switched-cancel low-pass filter circuit and a clock synchronization circuit, which eliminates the need for a sample-and-hold circuit and contributes to cost reduction. It is expected that Furthermore, since it can serve as both a deglitch circuit and a low-pass filter, the substrate can be made smaller and is expected to contribute to LSI implementation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram with a glitch, FIG. 3 is a block diagram showing a conventional technique, and FIG. 4 shows a timing signal, a first clock signal, and a second clock signal. FIG. 2 is a waveform diagram showing the relationship between clock signals of FIG. 4.10...D/A conversion circuit, 5...Sample hold circuit, 6...Low pass filter circuit, 11...Switched capacitor low pass filter circuit, 12...Clock synchronization circuit. Patent Applicant: Oki Electric Industry Co., Ltd. Figure 1 Figure 2 Figure 3 Figure 4 Procedural Amendment (Mutsu) , 8ゎ, 480.1.

Claims (1)

[Claims] In a D/A conversion output glitch removal circuit for removing glitches that occur when a digital signal is converted into an analog signal by a D/A conversion circuit, a timing signal from the D/A conversion circuit and a timing signal from the D/A conversion circuit are provided. , and a first clock signal synchronized with this timing signal, the glitch having a period longer than twice the pre-known maximum value of the time during which the output of the D/A conversion circuit deviates from the standard due to the glitch. Consisting of a clock synchronization circuit that outputs a second clock signal synchronized with the signal, and a switched capacitor low-pass filter circuit that selectively connects the input from the D/A conversion circuit according to the second clock signal, Glitch removal from the D/A conversion output, characterized in that during 1/2 period of the second clock, the switched capacitor low-pass filter circuit removes glitches without connecting the input from the conversion circuit to the D/A. circuit.