JPH01149129U - - Google Patents
Info
- Publication number
- JPH01149129U JPH01149129U JP1988046334U JP4633488U JPH01149129U JP H01149129 U JPH01149129 U JP H01149129U JP 1988046334 U JP1988046334 U JP 1988046334U JP 4633488 U JP4633488 U JP 4633488U JP H01149129 U JPH01149129 U JP H01149129U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- self
- signal
- oscillation
- pulse signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 230000003111 delayed effect Effects 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 claims 2
- 230000001934 delay Effects 0.000 claims 1
- 230000010355 oscillation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Pulse Circuits (AREA)
Description
第１図は本考案の遅延信号発生回路を示す回路
図、第２図は第１図の各部波形を示すタイミング
チヤート、第３図は従来の遅延信号発生回路を示
す回路図、第４図は第３図の各部波形を示すタイ
ミングチヤートである。
１３……自己発振回路、１７……分周回路、２
１……遅延回路。
Fig. 1 is a circuit diagram showing the delayed signal generation circuit of the present invention, Fig. 2 is a timing chart showing the waveforms of each part of Fig. 1, Fig. 3 is a circuit diagram showing the conventional delay signal generation circuit, and Fig. 4 is 4 is a timing chart showing waveforms of various parts in FIG. 3. FIG. 13... Self-oscillation circuit, 17... Frequency dividing circuit, 2
1...Delay circuit.
Claims (1)
信号を出力する自己発振回路と、前記発振信号を
分周して分周信号を出力するＮ段（Ｎ：自然数）
の分周回路と、前記パルス信号及び前記分周信号
に基づいて、前記パルス信号の立上り又は立下り
を遅延して遅延信号を出力する遅延回路とを設け
たことを特徴とする遅延信号発生回路。 (2) 前記自己発振回路は、論理回路及びコンデ
ンサより成り、前記論理回路のインピーダンス及
び前記コンデンサの負荷容量で定まる時定数を有
することを特徴とする請求項(1)記載の遅延信号
発生回路。[Claims for Utility Model Registration] (1) A self-oscillation circuit that self-oscillates and outputs an oscillation signal based on a pulse signal, and N stages (N: Natural number)
and a delay circuit that delays the rise or fall of the pulse signal and outputs a delayed signal based on the pulse signal and the frequency-divided signal. . (2) The delay signal generation circuit according to claim 1, wherein the self-oscillation circuit is composed of a logic circuit and a capacitor, and has a time constant determined by the impedance of the logic circuit and the load capacity of the capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988046334U JPH01149129U (en) | 1988-04-06 | 1988-04-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988046334U JPH01149129U (en) | 1988-04-06 | 1988-04-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01149129U true JPH01149129U (en) | 1989-10-16 |
Family
ID=31272605
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988046334U Pending JPH01149129U (en) | 1988-04-06 | 1988-04-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01149129U (en) |
-
1988
- 1988-04-06 JP JP1988046334U patent/JPH01149129U/ja active Pending