JPS61119486U - - Google Patents

Info

Publication number
JPS61119486U
JPS61119486U JP193085U JP193085U JPS61119486U JP S61119486 U JPS61119486 U JP S61119486U JP 193085 U JP193085 U JP 193085U JP 193085 U JP193085 U JP 193085U JP S61119486 U JPS61119486 U JP S61119486U
Authority
JP
Japan
Prior art keywords
comparator
hold circuit
peak hold
pulse signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP193085U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP193085U priority Critical patent/JPS61119486U/ja
Publication of JPS61119486U publication Critical patent/JPS61119486U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Measurement Of Unknown Time Intervals (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一例の構成図、第2図はその
説明のための図、第3図は、第4図は従来の装置
の説明のための図である。 21は入力端子、22,26はピークホールド
回路を構成するアンプ、27はコンデンサ、29
,37は出力端子、32はコンパレータ、34,
35は微分回路を構成する素子、36はアナログ
スイツチである。
FIG. 1 is a block diagram of an example of the present invention, FIG. 2 is a diagram for explaining the same, and FIGS. 3 and 4 are diagrams for explaining a conventional device. 21 is an input terminal, 22 and 26 are amplifiers forming a peak hold circuit, 27 is a capacitor, 29
, 37 is an output terminal, 32 is a comparator, 34,
35 is an element constituting a differential circuit, and 36 is an analog switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] パルス信号の所定レベル以上の期間を判別する
コンパレータと、上記パルス信号の波高値を保持
するピークホールド回路とを有し、上記コンパレ
ータの出力の立上がりエツジで上記ピークホール
ド回路をリセツトし、上記コンパレータの出力を
後段回路へ測定のタイミング信号として供給する
ようにしたパルス波測定回路。
It has a comparator that determines the period when the pulse signal is at a predetermined level or higher, and a peak hold circuit that holds the peak value of the pulse signal, and the peak hold circuit is reset at the rising edge of the output of the comparator, A pulse wave measurement circuit whose output is supplied to subsequent circuits as a measurement timing signal.
JP193085U 1985-01-11 1985-01-11 Pending JPS61119486U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP193085U JPS61119486U (en) 1985-01-11 1985-01-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP193085U JPS61119486U (en) 1985-01-11 1985-01-11

Publications (1)

Publication Number Publication Date
JPS61119486U true JPS61119486U (en) 1986-07-28

Family

ID=30475125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP193085U Pending JPS61119486U (en) 1985-01-11 1985-01-11

Country Status (1)

Country Link
JP (1) JPS61119486U (en)

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