JPS6286730U - - Google Patents
Info
- Publication number
- JPS6286730U JPS6286730U JP17772785U JP17772785U JPS6286730U JP S6286730 U JPS6286730 U JP S6286730U JP 17772785 U JP17772785 U JP 17772785U JP 17772785 U JP17772785 U JP 17772785U JP S6286730 U JPS6286730 U JP S6286730U
- Authority
- JP
- Japan
- Prior art keywords
- digital signal
- transistor
- receives
- base
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000007493 shaping process Methods 0.000 claims 2
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の一実施例によるデジタル信号
受信回路のブロツク図、第２図ａ，ｂ，ｃは本考
案の説明に付する各部の波形図、第３図は従来の
信号受信回路のブロツク図である。
１……トランジスタ、２……抵抗器、３……コ
ンデンサ。
Fig. 1 is a block diagram of a digital signal receiving circuit according to an embodiment of the present invention, Fig. 2 a, b, and c are waveform diagrams of various parts to explain the present invention, and Fig. 3 is a diagram of a conventional signal receiving circuit. It is a block diagram. 1...transistor, 2...resistor, 3...capacitor.
Claims (1)
号をベースに受け、抵抗器とコンデンサで形成さ
れる積分回路をコレクタに接続されたトランジス
タと、この積分回路により積分された前記デジタ
ル信号のうち、設定したスレツシユホールドレベ
ルを超えるもののみを整形するようにした波形整
形回路と、この波形整形回路の出力によりデジタ
ル信号の処理を行なう信号処理部とよりなるデジ
タル信号受信回路。 A digital signal receiving section, a transistor that receives the received digital signal as a base, and has an integrating circuit formed of a resistor and a capacitor connected to its collector, and a transistor that receives the received digital signal as a base, and a transistor that receives the received digital signal as a base, and has a transistor connected to the collector, and a set of the digital signals integrated by this integrating circuit. A digital signal receiving circuit consisting of a waveform shaping circuit that shapes only those exceeding a threshold level, and a signal processing section that processes digital signals using the output of this waveform shaping circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17772785U JPS6286730U (en) | 1985-11-19 | 1985-11-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17772785U JPS6286730U (en) | 1985-11-19 | 1985-11-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6286730U true JPS6286730U (en) | 1987-06-03 |
Family
ID=31119202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17772785U Pending JPS6286730U (en) | 1985-11-19 | 1985-11-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6286730U (en) |
-
1985
- 1985-11-19 JP JP17772785U patent/JPS6286730U/ja active Pending