JPH0365356U - - Google Patents

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Publication number
JPH0365356U
JPH0365356U JP12759789U JP12759789U JPH0365356U JP H0365356 U JPH0365356 U JP H0365356U JP 12759789 U JP12759789 U JP 12759789U JP 12759789 U JP12759789 U JP 12759789U JP H0365356 U JPH0365356 U JP H0365356U
Authority
JP
Japan
Prior art keywords
synchronization signal
reference level
circuit
signal
peak detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12759789U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12759789U priority Critical patent/JPH0365356U/ja
Publication of JPH0365356U publication Critical patent/JPH0365356U/ja
Pending legal-status Critical Current

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  • Synchronizing For Television (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す図、第2図は
その波形図である。第3図第4図は夫々従来例を
示す図である。 10……同期信号入力端子、16……比較器(
比較回路)、20……ピーク検出回路、24……
基準レベル作成回路。
FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram thereof. 3 and 4 are diagrams showing conventional examples, respectively. 10... Synchronization signal input terminal, 16... Comparator (
comparison circuit), 20... peak detection circuit, 24...
Reference level creation circuit.

Claims (1)

【実用新案登録請求の範囲】 同期信号入力端子10からの同期信号と基準レ
ベル信号とを比較する比較回路16を備える同期
信号整形回路に於いて、 前記同期信号のピーク値を検出するピーク検出
回路20と、 このピーク検出回路20からの出力信号を分圧
して前記基準レベル信号を作成する基準レベル作
成回路24と、 を備えることを特徴とする同期信号整形回路。
[Claims for Utility Model Registration] In a synchronization signal shaping circuit comprising a comparison circuit 16 for comparing a synchronization signal from a synchronization signal input terminal 10 and a reference level signal, a peak detection circuit for detecting a peak value of the synchronization signal. 20; and a reference level creation circuit 24 that divides the output signal from the peak detection circuit 20 to create the reference level signal.
JP12759789U 1989-10-31 1989-10-31 Pending JPH0365356U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12759789U JPH0365356U (en) 1989-10-31 1989-10-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12759789U JPH0365356U (en) 1989-10-31 1989-10-31

Publications (1)

Publication Number Publication Date
JPH0365356U true JPH0365356U (en) 1991-06-25

Family

ID=31675349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12759789U Pending JPH0365356U (en) 1989-10-31 1989-10-31

Country Status (1)

Country Link
JP (1) JPH0365356U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741325B2 (en) * 1973-10-24 1982-09-02

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5741325B2 (en) * 1973-10-24 1982-09-02

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