JPS6433230U - - Google Patents
Info
- Publication number
- JPS6433230U JPS6433230U JP12748887U JP12748887U JPS6433230U JP S6433230 U JPS6433230 U JP S6433230U JP 12748887 U JP12748887 U JP 12748887U JP 12748887 U JP12748887 U JP 12748887U JP S6433230 U JPS6433230 U JP S6433230U
- Authority
- JP
- Japan
- Prior art keywords
- converter
- signal level
- limiting circuit
- output
- arbitrary function
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 9
Landscapes
- Analogue/Digital Conversion (AREA)
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
第１図乃至第３図は、この考案に係る振幅制限
回路の実施例を示すものであつて、第１図は全体
構成を示すブロツク図、第２図は第１図の振幅制
限回路の入出力特性図、第３図は第１図の振幅制
限回路の応用例を示すブロツク図である。第４図
乃至第７図は、従来例を示すものであつて、第４
図は回路図、第５図は第４図の振幅制限回路の入
出力特性図、第６図はブロツク図、第７図は第６
図の振幅制限回路の入出力特性図である。
主な図番の説明、１０：Ａ／Ｄコンバータ、１
１：基準電圧発生器、１２：信号レベル検出器、
１３：任意関数発生器。
1 to 3 show an embodiment of the amplitude limiting circuit according to the invention, FIG. 1 is a block diagram showing the overall configuration, and FIG. 2 is an input diagram of the amplitude limiting circuit of FIG. 1. The output characteristic diagram, FIG. 3, is a block diagram showing an example of application of the amplitude limiting circuit of FIG. 4 to 7 show conventional examples.
The figure is a circuit diagram, Figure 5 is an input/output characteristic diagram of the amplitude limiting circuit in Figure 4, Figure 6 is a block diagram, and Figure 7 is a diagram of the input/output characteristics of the amplitude limiting circuit in Figure 4.
FIG. 3 is an input/output characteristic diagram of the amplitude limiting circuit shown in the figure. Explanation of main figure numbers, 10: A/D converter, 1
1: Reference voltage generator, 12: Signal level detector,
13: Arbitrary function generator.
Claims (1)
力信号をＡ／Ｄ変換するＡ／Ｄコンバータと、こ
のＡ／Ｄコンバータの入力信号レベルを検出する
信号レベル検出器と、この信号レベル検出器の検
出信号に応じて任意の関数を発生し前記基準電圧
発生器を制御する任意関数発生器とを備えたこと
を特徴とする振幅制限回路。 (2) 前記任意関数発生器の関数を変更可能に構
成し、Ａ／Ｄコンバータの入出力特性（振幅制御
特性）を自由に設定することができるようにした
ことを特徴とする実用新案登録請求の範囲第１項
記載の振幅制限回路。 (3) 前記Ａ／Ｄコンバータの出力に、Ｄ／Ａコ
ンバータを備えたことを特徴とする実用新案登録
請求の範囲第１項記載の振幅制限回路。[Claims for Utility Model Registration] (1) An A/D converter that A/D converts an input signal using the output signal of a reference voltage generator as a reference, and a signal level detector that detects the input signal level of this A/D converter. and an arbitrary function generator that generates an arbitrary function according to the detection signal of the signal level detector and controls the reference voltage generator. (2) A request for registration of a utility model characterized in that the function of the arbitrary function generator is configured to be changeable, and the input/output characteristics (amplitude control characteristics) of the A/D converter can be freely set. The amplitude limiting circuit according to item 1. (3) The amplitude limiting circuit according to claim 1, which is characterized in that a D/A converter is provided at the output of the A/D converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12748887U JPS6433230U (en) | 1987-08-24 | 1987-08-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12748887U JPS6433230U (en) | 1987-08-24 | 1987-08-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6433230U true JPS6433230U (en) | 1989-03-01 |
Family
ID=31379969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12748887U Pending JPS6433230U (en) | 1987-08-24 | 1987-08-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6433230U (en) |
-
1987
- 1987-08-24 JP JP12748887U patent/JPS6433230U/ja active Pending