JPS61161792U - - Google Patents
Info
- Publication number
- JPS61161792U JPS61161792U JP1985046064U JP4606485U JPS61161792U JP S61161792 U JPS61161792 U JP S61161792U JP 1985046064 U JP1985046064 U JP 1985046064U JP 4606485 U JP4606485 U JP 4606485U JP S61161792 U JPS61161792 U JP S61161792U
- Authority
- JP
- Japan
- Prior art keywords
- presettable counter
- data
- register
- time
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electric Clocks (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図は従来例を示す図であり、図において１
は発振回路、２はプリセツタブルカウンタ、３は
第１のレジスタ、４はデイジタル比較器、５は第
２のレジスタ、６は加減算回路である。尚、図中
において同一又は相当部分には同一番号を付して
ある。
Fig. 1 is a block diagram showing an embodiment of this invention, and Fig. 2 is a diagram showing a conventional example.
2 is an oscillation circuit, 2 is a presettable counter, 3 is a first register, 4 is a digital comparator, 5 is a second register, and 6 is an addition/subtraction circuit. In addition, the same numbers are attached to the same or corresponding parts in the figures.
Claims (1)
回路より与えられるクロツク信号により時刻を計
数するプリセツタブルカウンタと、時刻の周期デ
ータを格納する第１のレジスタと、この第１のレ
ジスタの内容と上記プリセツタブルカウンタの出
力として得られる時刻符号データを比較し、両者
の一致時点に上記プリセツタブルカウンタに対し
てリセツトパルスを出力するデイジタル比較回路
と、外部より与えられる時刻補正データを格納す
る第２のレジスタと、この第２のレジスタの出力
データと上記プリセツタブルカウンタより出力さ
れる時刻符号データの加減演算を行い、その結果
を上記プリセツタブルカウンタのロードデータと
して出力する加算回路とを備えたことを特徴とす
る時刻符号発生器。 An oscillation circuit as a clock signal source, a presettable counter that counts time using a clock signal provided by the oscillation circuit, a first register that stores time cycle data, and the contents of this first register and the above. A digital comparison circuit that compares the time code data obtained as the output of the presettable counter and outputs a reset pulse to the presettable counter when the two match, and a digital comparison circuit that stores the time correction data given from the outside. and an addition circuit that performs an addition/subtraction operation on the output data of the second register and the time code data output from the presettable counter, and outputs the result as load data for the presettable counter. A time code generator comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985046064U JPS61161792U (en) | 1985-03-29 | 1985-03-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985046064U JPS61161792U (en) | 1985-03-29 | 1985-03-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61161792U true JPS61161792U (en) | 1986-10-07 |
Family
ID=30560122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985046064U Pending JPS61161792U (en) | 1985-03-29 | 1985-03-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61161792U (en) |
-
1985
- 1985-03-29 JP JP1985046064U patent/JPS61161792U/ja active Pending
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