JPH02138925U - - Google Patents
Info
- Publication number
- JPH02138925U JPH02138925U JP1989047905U JP4790589U JPH02138925U JP H02138925 U JPH02138925 U JP H02138925U JP 1989047905 U JP1989047905 U JP 1989047905U JP 4790589 U JP4790589 U JP 4790589U JP H02138925 U JPH02138925 U JP H02138925U
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- logic
- generates
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Description
第1図は、この考案を適用した一実施例のパル
ス幅変調信号発生回路のブロツク図、第2図は、
その動作のタイミングチヤート、第3図は、従来
のパルス幅変調信号発生回路の動作の一例の説明
図である。
1……PWM信号発生回路、2……PWMカウ
ンタ、3……比較データ発生回路、4……一致検
出回路、5……補正出力回路、6……PWM信号
生成回路。
FIG. 1 is a block diagram of a pulse width modulation signal generation circuit according to an embodiment of this invention, and FIG.
The timing chart of the operation, FIG. 3, is an explanatory diagram of an example of the operation of the conventional pulse width modulation signal generation circuit. 1... PWM signal generation circuit, 2... PWM counter, 3... Comparison data generation circuit, 4... Coincidence detection circuit, 5... Correction output circuit, 6... PWM signal generation circuit.
Claims (1)
ント値がカウントアツプして循環するn進カウン
タ(nは2以上の整数)と、このn進カウンタの
選択された連続する各桁に対応してビツトパラレ
ルに比較データを発生する比較データ発生回路と
、前記n進カウンタの選択された連続する各桁の
値をAとし、前記比較データ発生回路の前記各桁
対応のビツト値をBとしたときC=A+の論理
操作をしてCの出力を発生する論理操作回路を前
記各桁対応に有していてこれら論理操作回路の論
理値の出力Cの論理積の出力を発生する第1の論
理回路と、前記n進カウンタの選択された桁のう
ちの最上位桁の出力の値をDとし、前記比較デー
タ発生回路の最上位桁の出力の値をEとしたとき
F=D・の論理操作をしてFの出力を発生する
論理操作回路を有し、この論理操作回路の出力F
と第1の論理回路の出力との論理和の出力を発生
する第2の論理回路と、この第2の論理回路の出
力と前記n進カウンタの出力とを受けて前記比較
データがn進カウンタの値以下のとき及び以上の
ときのいずれか一方に対応する期間の間、論理レ
ベルで“1”或は“0”となる信号を発生するパ
ルス発生回路とを備えることを特徴とするパルス
幅変調信号発生回路。 An n-ary counter (n is an integer of 2 or more) that receives a clock and counts it, and the count value is counted up and circulated, and a bit parallel counter corresponding to each consecutive selected digit of this n-ary counter. A comparison data generation circuit that generates comparison data, A is the value of each selected consecutive digit of the n-ary counter, and B is a bit value corresponding to each digit of the comparison data generation circuit, then C= A first logic circuit, which has a logic operation circuit corresponding to each of the digits, which performs a logic operation on A+ and generates an output of C, and generates an output of a logical product of outputs C of the logic values of these logic operation circuits; , the value of the output of the most significant digit of the selected digits of the n-ary counter is D, and the value of the output of the most significant digit of the comparison data generation circuit is E, then the logical operation of F=D. has a logic operation circuit that generates an output of F, and the output of this logic operation circuit is F.
and an output of the first logic circuit; and a second logic circuit that generates an output of the logical sum of and a pulse generating circuit that generates a signal whose logic level is "1" or "0" during a period corresponding to either one of the values below and above the value. Modulation signal generation circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989047905U JPH0728738Y2 (en) | 1989-04-24 | 1989-04-24 | Pulse width modulation signal generation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989047905U JPH0728738Y2 (en) | 1989-04-24 | 1989-04-24 | Pulse width modulation signal generation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02138925U true JPH02138925U (en) | 1990-11-20 |
JPH0728738Y2 JPH0728738Y2 (en) | 1995-06-28 |
Family
ID=31564247
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989047905U Expired - Lifetime JPH0728738Y2 (en) | 1989-04-24 | 1989-04-24 | Pulse width modulation signal generation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0728738Y2 (en) |
-
1989
- 1989-04-24 JP JP1989047905U patent/JPH0728738Y2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0728738Y2 (en) | 1995-06-28 |
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