JPS596338U - counter circuit - Google Patents
counter circuitInfo
- Publication number
- JPS596338U JPS596338U JP10111982U JP10111982U JPS596338U JP S596338 U JPS596338 U JP S596338U JP 10111982 U JP10111982 U JP 10111982U JP 10111982 U JP10111982 U JP 10111982U JP S596338 U JPS596338 U JP S596338U
- Authority
- JP
- Japan
- Prior art keywords
- counter
- supplied
- counter circuit
- circuit
- oscillation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示す回路図、第２図はその
一部の具体構成婆示す回路図、第３図は波形図、第４〜
第１７図は本考案の他の実施例の検出回路の部分を示す
回路図、第１８図は本考案を応用した応用回路を示す回
路図、第１９図は波形図である。
１はＭ進カウンタ、５は検出回路、２０は発振回路であ
る。
第１８図
第１９図Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a part of the specific configuration, Fig. 3 is a waveform diagram, and Fig. 4 -
FIG. 17 is a circuit diagram showing a portion of a detection circuit according to another embodiment of the present invention, FIG. 18 is a circuit diagram showing an applied circuit to which the present invention is applied, and FIG. 19 is a waveform diagram. 1 is an M-ary counter, 5 is a detection circuit, and 20 is an oscillation circuit. Figure 18 Figure 19
Claims (1)
出回路と、上記カウンタに供給するクロック信号の周波
数より充分高い周波数の発振信号を発生する発振回路と
を有し、上記計数値Ｘが０≦Ｘ＜Ｎ（２≦Ｎ＜Ｍ） のとき、上記クロック信号を上記カウンタに供給して計
数せしめ Ｎ≦Ｘ＜Ｍ のとき上記発振信号を上記カウンタに供給して急速に計
数せしめることにより、上記カウンタをＮ進カウンタと
して動作せしめるようにしたことを特徴とするカウンタ
回路。[Claims for Utility Model Registration] An M-adic counter, a detection circuit for detecting the count value X of the counter, and an oscillation circuit for generating an oscillation signal with a frequency sufficiently higher than the frequency of the clock signal supplied to the counter. and when the count value X is 0≦X<N (2≦N<M), the clock signal is supplied to the counter for counting, and when N≦X<M, the oscillation signal is supplied to the counter. A counter circuit characterized in that the counter is operated as an N-ary counter by causing rapid counting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10111982U JPS596338U (en) | 1982-07-02 | 1982-07-02 | counter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10111982U JPS596338U (en) | 1982-07-02 | 1982-07-02 | counter circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS596338U true JPS596338U (en) | 1984-01-17 |
Family
ID=30238923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10111982U Pending JPS596338U (en) | 1982-07-02 | 1982-07-02 | counter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596338U (en) |
-
1982
- 1982-07-02 JP JP10111982U patent/JPS596338U/en active Pending
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