JPS58184964U - Facsimile procedure interruption signal detection circuit - Google Patents
Facsimile procedure interruption signal detection circuitInfo
- Publication number
- JPS58184964U JPS58184964U JP8110282U JP8110282U JPS58184964U JP S58184964 U JPS58184964 U JP S58184964U JP 8110282 U JP8110282 U JP 8110282U JP 8110282 U JP8110282 U JP 8110282U JP S58184964 U JPS58184964 U JP S58184964U
- Authority
- JP
- Japan
- Prior art keywords
- interruption signal
- detection circuit
- signal detection
- facsimile procedure
- procedure interruption
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Facsimile Transmission Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例を示すブロック図、第２図ａ。
ｃ ” ｈはその動作を示す波形図、第３図は本考案の
実施例を示すブロック図、第２図すはその動作を示す波
形図である。
１はハイブリッドトランス、２は増幅器、３゜４はバイ
パスフィルタ（不要帯域ノイズ除去）、５は帯域除去フ
ィルタ（キャリア成分除去）、６はリミッタ・アンプ、
７は比較回路、８はバイパスフィルタ（ＰＩＳ同調用）
、９は積分回路、１０はコンパレータ、１５は位相信号
送出用カウンタ、１６はドライバ、１１はコンパレータ
の出力信号、１７は位相周期をつくるカウンタに入力さ
せる精 ７度の高いクロックを発生する発振回路である
。FIG. 1 is a block diagram showing a conventional example, and FIG. 2a. c ”h is a waveform diagram showing its operation, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 2 is a waveform diagram showing its operation. 1 is a hybrid transformer, 2 is an amplifier, 3° 4 is a bypass filter (removes unnecessary band noise), 5 is a band elimination filter (removes carrier components), 6 is a limiter amplifier,
7 is a comparison circuit, 8 is a bypass filter (for PIS tuning)
, 9 is an integrator circuit, 10 is a comparator, 15 is a phase signal sending counter, 16 is a driver, 11 is an output signal of the comparator, and 17 is an oscillation circuit that generates a clock with a high precision of 7 degrees to be input to the counter that creates the phase cycle. It is.
Claims (1)
信号を検出するための、受信位相信号を発生する回路と
放電回路とを有することを特徴とするファクシミリの手
順中断信号検出回路。 ゛A facsimile procedure interruption signal detection circuit comprising a receiving phase signal generating circuit and a discharging circuit for detecting a facsimile procedure interruption signal having CCITTG2 mode.゛
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8110282U JPS58184964U (en) | 1982-06-01 | 1982-06-01 | Facsimile procedure interruption signal detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8110282U JPS58184964U (en) | 1982-06-01 | 1982-06-01 | Facsimile procedure interruption signal detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58184964U true JPS58184964U (en) | 1983-12-08 |
Family
ID=30090231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8110282U Pending JPS58184964U (en) | 1982-06-01 | 1982-06-01 | Facsimile procedure interruption signal detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58184964U (en) |
-
1982
- 1982-06-01 JP JP8110282U patent/JPS58184964U/en active Pending
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