JPS61176809U - - Google Patents
Info
- Publication number
- JPS61176809U JPS61176809U JP5751985U JP5751985U JPS61176809U JP S61176809 U JPS61176809 U JP S61176809U JP 5751985 U JP5751985 U JP 5751985U JP 5751985 U JP5751985 U JP 5751985U JP S61176809 U JPS61176809 U JP S61176809U
- Authority
- JP
- Japan
- Prior art keywords
- phase
- utility
- model registration
- variable device
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Networks Using Active Elements (AREA)
Description
第1図は本考案のブロツク図、第2図は従来の
ブロツク図、第3図はタイミングチヤートである
。
1……基本クロツク、2……カウンタ、3……
CPU、4……位相設定レジスタ、5……加算器
、6……ROM、7……AD変換器、8……フイ
ルタ、9……増巾器、10……カウンタの出力、
11……CPUからのデータバス、12……位相
設定レジスタの出力バス、13……加算器の出力
、ROMのアドレスバス、14……ROMのデー
タバス。
FIG. 1 is a block diagram of the present invention, FIG. 2 is a conventional block diagram, and FIG. 3 is a timing chart. 1...Basic clock, 2...Counter, 3...
CPU, 4... Phase setting register, 5... Adder, 6... ROM, 7... AD converter, 8... Filter, 9... Amplifier, 10... Counter output,
11...Data bus from CPU, 12...Output bus of phase setting register, 13...Output of adder, ROM address bus, 14...Data bus of ROM.
Claims (1)
器、フイルター、増巾器、クロツクより成る任意
の周波数を発生する回路において、位相設定器と
加算器をそなえることによつて、任意の周波数と
位相を発生させることを特徴とする位相可変器。 2 位相設定をデイジタル的に行なうことにより
、CPUより容易に設定でき、再設定も容易であ
ることを特徴とする実用新案登録請求の範囲第1
項記載の位相可変器。[Claims for Utility Model Registration] 1. A circuit that generates an arbitrary frequency and is composed of a ROM in which the value of a sine function is written, an AD converter, a filter, an amplifier, and a clock, and is equipped with a phase setter and an adder. Therefore, a phase variable device is characterized in that it can generate any frequency and phase. 2. Utility model registration claim 1, which is characterized in that by digitally setting the phase, it can be set more easily than by a CPU, and resetting is also easier.
Phase variable device as described in section.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5751985U JPS61176809U (en) | 1985-04-19 | 1985-04-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5751985U JPS61176809U (en) | 1985-04-19 | 1985-04-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61176809U true JPS61176809U (en) | 1986-11-05 |
Family
ID=30582126
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5751985U Pending JPS61176809U (en) | 1985-04-19 | 1985-04-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61176809U (en) |
-
1985
- 1985-04-19 JP JP5751985U patent/JPS61176809U/ja active Pending
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