JPS6214855U - - Google Patents
Info
- Publication number
- JPS6214855U JPS6214855U JP1985107075U JP10707585U JPS6214855U JP S6214855 U JPS6214855 U JP S6214855U JP 1985107075 U JP1985107075 U JP 1985107075U JP 10707585 U JP10707585 U JP 10707585U JP S6214855 U JPS6214855 U JP S6214855U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output
- decode output
- synchronization
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Description
第１図は本考案の一実施例を示す回路ブロツク
図、第２図は同要部回路ブロツク図を、それぞれ
示す。
主な図番の説明、１……固定発振回路、２……
第１分周回路、３……同期信号発生回路、４……
第２分周回路、５……カウンタ、６，７，８……
第１・第２・第３デコーダ、９……第３分周回路
、１０……水平転送クロツク発生回路、１２……
クロツク発生回路。
FIG. 1 is a circuit block diagram showing an embodiment of the present invention, and FIG. 2 is a circuit block diagram of the main part thereof. Explanation of main figure numbers, 1...Fixed oscillation circuit, 2...
First frequency dividing circuit, 3... Synchronization signal generation circuit, 4...
Second frequency dividing circuit, 5... Counter, 6, 7, 8...
1st, 2nd, and 3rd decoders, 9...Third frequency dividing circuit, 10...Horizontal transfer clock generation circuit, 12...
Clock generation circuit.
Claims (1)
る第１分周回路と、 前記マスタクロツクを計数入力とし外部より入
力される水平同期パルスと垂直同期パルスとをリ
セツト入力とし同期信号を発生する同期信号発生
回路と、 前記水平同期パルスの立下りに同期して前記マ
スタクロツクを分周する第２分周回路と、 該第２分周出力を計数するカウンタと、 該カウンタ出力に基づき第１デコード出力と第
２デコード出力と第３デコード出力を順に導出し
、該第３デコード出力発生時に前記第２分周回路
を不作動とするデコーダと、 前記第２デコード出力をリセツト入力とし前記
固定発振出力を分周する第３分周回路と、 前記第３デコード出力に同期して前記第３分周
出力の分周を開始し第１デコード出力に同期して
分周動作を停止する水平転送クロツク発生回路と
を、 それぞれ配して成る固体撮像素子の外部同期回
路。[Claims for Utility Model Registration] A first frequency dividing circuit that divides the frequency of a fixed oscillation output to generate a master clock, and synchronizes with the master clock as a counting input and horizontal synchronization pulses and vertical synchronization pulses input from the outside as reset inputs. a synchronous signal generating circuit that generates a signal; a second frequency dividing circuit that divides the frequency of the master clock in synchronization with the falling edge of the horizontal synchronous pulse; a counter that counts the second frequency-divided output; a decoder that sequentially derives a first decode output, a second decode output, and a third decode output based on the decode output, and disables the second frequency dividing circuit when the third decode output is generated; and the second decode output is used as a reset input. a third frequency dividing circuit that divides the frequency of the fixed oscillation output; and a third frequency dividing circuit that starts dividing the third frequency divided output in synchronization with the third decode output and stops the frequency division operation in synchronization with the first decode output. An external synchronization circuit for a solid-state image sensor, consisting of a horizontal transfer clock generation circuit and a horizontal transfer clock generation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985107075U JPS6214855U (en) | 1985-07-12 | 1985-07-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985107075U JPS6214855U (en) | 1985-07-12 | 1985-07-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6214855U true JPS6214855U (en) | 1987-01-29 |
Family
ID=30983016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985107075U Pending JPS6214855U (en) | 1985-07-12 | 1985-07-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6214855U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59193671A (en) * | 1983-04-18 | 1984-11-02 | Matsushita Electric Ind Co Ltd | External synchronizing method of solid-state image pickup device |
-
1985
- 1985-07-12 JP JP1985107075U patent/JPS6214855U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59193671A (en) * | 1983-04-18 | 1984-11-02 | Matsushita Electric Ind Co Ltd | External synchronizing method of solid-state image pickup device |