JPH03125561U

JPH03125561U -

Info

Publication number: JPH03125561U
Application number: JP3414090U
Authority: JP
Priority date: 1990-03-30
Filing date: 1990-03-30
Publication date: 1991-12-18

Description

[Brief explanation of the drawing]

第１図は、この考案の疑似同期信号発生装置の
一実施例を示す回路構成図、第２図は、第１図に
示した回路各部の信号波形図、第３図は、従来の
疑似同期信号発生装置を適用したマルチスキヤン
方式デイスプレイ装置の一例を示す回路構成図、
第４図は、第３図に示した回路各部の信号波形図
である。１１……疑似同期信号発生装置、１２……倍周
回路、１３……プログラマブル・カウンタ回路、
１４……表示画位置調整回路。 Fig. 1 is a circuit configuration diagram showing an embodiment of the pseudo synchronous signal generator of this invention, Fig. 2 is a signal waveform diagram of each part of the circuit shown in Fig. 1, and Fig. 3 is a conventional pseudo synchronous signal generator. A circuit configuration diagram showing an example of a multi-scan display device using a signal generator;
FIG. 4 is a signal waveform diagram of each part of the circuit shown in FIG. 3. 11... Pseudo synchronous signal generator, 12... Frequency doubler circuit, 13... Programmable counter circuit,
14...Display image position adjustment circuit.

Claims

[Scope of utility model registration request]

A frequency doubling circuit that doubles the frequency of a synchronization signal accompanying a video signal by a predetermined frequency ratio to generate a clock signal having a period corresponding to the unit movement distance of the display image; Step counting is performed in accordance with the clock signal from the initial counting value set in Programmable output that outputs a carry signal that determines the phase.
A pseudo synchronization signal generating device comprising a counter circuit and a display image position adjustment circuit for varying the initial count value set in the programmable counter circuit and arbitrarily adjusting the display image position.