JPH0377564U - - Google Patents

Description

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention;
3 and 3 are timing charts for explaining the operation of the same embodiment, FIG. 4 is a block diagram showing a conventional gradation timing signal generation circuit, and FIG. 5 shows a general gradation signal generation circuit. Figure 6 is the 4th
This is a timing chart for explaining the operation shown in the figure. 31, 38, 39, 48... flip-flop, 33, 35, 37, 43, 44, 50... counter, 41... latch circuit.

Claims (1)

[Scope of utility model registration request] A frequency dividing means that divides the basic clock by n, a first counter that counts the clock frequency divided by the frequency dividing means in units of one horizontal period, and a count value of this counter is sequentially latched every horizontal period. a second counter for counting basic clock pulses; a coincidence detecting means for detecting a coincidence by comparing the count value of the second counter with a value held in the latch means; clock output means for outputting an n-divided clock every time a match is detected by the means; means for resetting the second counter each time the n-divided clock is output from the clock output means; 1. A gradation timing signal generation circuit comprising: gradation timing signal generation means for generating a gradation timing signal based on an outputted n-divided clock.