JPS6136573U - Signal generation period measurement circuit - Google Patents

Signal generation period measurement circuit

Info

Publication number
JPS6136573U
JPS6136573U JP12213284U JP12213284U JPS6136573U JP S6136573 U JPS6136573 U JP S6136573U JP 12213284 U JP12213284 U JP 12213284U JP 12213284 U JP12213284 U JP 12213284U JP S6136573 U JPS6136573 U JP S6136573U
Authority
JP
Japan
Prior art keywords
signal generation
defines
measurement circuit
generation period
period measurement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12213284U
Other languages
Japanese (ja)
Inventor
渉 高橋
広重 坂原
聡 桜井
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP12213284U priority Critical patent/JPS6136573U/en
Publication of JPS6136573U publication Critical patent/JPS6136573U/en
Pending legal-status Critical Current

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  • Measuring Frequencies, Analyzing Spectra (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】 第1図は本考案の一実施例であり、第1図aは回路図、
第1図bはタイミングチャート、第2図は従来の測定回
路の一例で、第2図.aは回路図、第2図bはタイミン
グチャート、でiる。 図において、 1は分周器、2,11はパルス発生器、3はアツプカウ
ンタ、4はバッファ回路、5は表示器、9A,9Bは微
分器、1oは発光ダイオード、12は比較回路、13は
ワンショットマルチバイブレータ、である。
[Brief Description of the Drawings] Figure 1 shows an embodiment of the present invention, Figure 1a is a circuit diagram,
FIG. 1b is a timing chart, FIG. 2 is an example of a conventional measurement circuit, and FIG. 2a is a circuit diagram, and FIG. 2b is a timing chart. In the figure, 1 is a frequency divider, 2 and 11 are pulse generators, 3 is an up counter, 4 is a buffer circuit, 5 is a display, 9A and 9B are differentiators, 1o is a light emitting diode, 12 is a comparison circuit, and 13 is a one-shot multivibrator.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 信号発生周期に対応してカウントエリャを規定する信号
を発生する分周器と、最小測定周期値を規定するパルス
発生器と、最大測定周期値を規定するパルス発生器と、
アツプカウンタ、バッファ回路および表示器からなる計
数回路と、入力信号製期と該最大測定周期値を比較する
比較回路を具えてなることを特徴とする信号発生周期測
定回路。
a frequency divider that generates a signal that defines a count area in response to a signal generation cycle; a pulse generator that defines a minimum measurement cycle value; and a pulse generator that defines a maximum measurement cycle value;
1. A signal generation cycle measuring circuit comprising a counting circuit comprising an up counter, a buffer circuit and a display, and a comparison circuit for comparing an input signal production period and the maximum measurement cycle value.
JP12213284U 1984-08-09 1984-08-09 Signal generation period measurement circuit Pending JPS6136573U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12213284U JPS6136573U (en) 1984-08-09 1984-08-09 Signal generation period measurement circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12213284U JPS6136573U (en) 1984-08-09 1984-08-09 Signal generation period measurement circuit

Publications (1)

Publication Number Publication Date
JPS6136573U true JPS6136573U (en) 1986-03-06

Family

ID=30680893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12213284U Pending JPS6136573U (en) 1984-08-09 1984-08-09 Signal generation period measurement circuit

Country Status (1)

Country Link
JP (1) JPS6136573U (en)

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