JPS6136573U

JPS6136573U - Signal generation period measurement circuit

Info

Publication number: JPS6136573U
Application number: JP12213284U
Authority: JP
Inventors: 渉高橋; 広重坂原; 聡桜井
Original assignee: 富士通株式会社
Priority date: 1984-08-09
Filing date: 1984-08-09
Publication date: 1986-03-06

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】第１図は本考案の一実施例であり、第１図ａは回路図、
第１図ｂはタイミングチャート、第２図は従来の測定回
路の一例で、第２図．ａは回路図、第２図ｂはタイミン
グチャート、でｉる。図において、１は分周器、２，１１はパルス発生器、３はアツプカウ
ンタ、４はバッファ回路、５は表示器、９Ａ，９Ｂは微
分器、１ｏは発光ダイオード、１２は比較回路、１３は
ワンショットマルチバイブレータ、である。[Brief Description of the Drawings] Figure 1 shows an embodiment of the present invention, Figure 1a is a circuit diagram,
FIG. 1b is a timing chart, FIG. 2 is an example of a conventional measurement circuit, and FIG. 2a is a circuit diagram, and FIG. 2b is a timing chart. In the figure, 1 is a frequency divider, 2 and 11 are pulse generators, 3 is an up counter, 4 is a buffer circuit, 5 is a display, 9A and 9B are differentiators, 1o is a light emitting diode, 12 is a comparison circuit, and 13 is a one-shot multivibrator.

Claims

[Scope of utility model registration request]

a frequency divider that generates a signal that defines a count area in response to a signal generation cycle; a pulse generator that defines a minimum measurement cycle value; and a pulse generator that defines a maximum measurement cycle value;
1. A signal generation cycle measuring circuit comprising a counting circuit comprising an up counter, a buffer circuit and a display, and a comparison circuit for comparing an input signal production period and the maximum measurement cycle value.