JPS59169134U - BBD delay time display device - Google Patents

BBD delay time display device

Info

Publication number
JPS59169134U
JPS59169134U JP6302783U JP6302783U JPS59169134U JP S59169134 U JPS59169134 U JP S59169134U JP 6302783 U JP6302783 U JP 6302783U JP 6302783 U JP6302783 U JP 6302783U JP S59169134 U JPS59169134 U JP S59169134U
Authority
JP
Japan
Prior art keywords
display device
delay time
time display
bbd
clock pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6302783U
Other languages
Japanese (ja)
Inventor
一博 林
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP6302783U priority Critical patent/JPS59169134U/en
Publication of JPS59169134U publication Critical patent/JPS59169134U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例よりなるＢＢＤの遅延時間表
示装置のブロック図、第２図は各部ａ〜ｄの波形図であ
る。 １〜４・・・ＢＣＤカウンタ、５〜８・・・ラッチ、９
・・・分周器、１０・・・パルス発生回路、１１・・・
パルス遅延回路、１２〜１５・・・数値表示素子。FIG. 1 is a block diagram of a BBD delay time display device according to an embodiment of the present invention, and FIG. 2 is a waveform diagram of each part a to d. 1-4...BCD counter, 5-8...latch, 9
... Frequency divider, 10... Pulse generation circuit, 11...
Pulse delay circuit, 12-15... Numerical display element.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＢＢＤを駆動するためのクロックパルス発生手段と、該
クロックパルスを分周するための手段と、該分周された
クロックパルスの１周期に基準周波数のパルス数をカウ
ントする手段と、および該カウントされたパルス数を表
示する手段とからなることを特徴とするＢＢＤの遅延時
間表示装置。A clock pulse generating means for driving the BBD, a means for dividing the frequency of the clock pulse, a means for counting the number of pulses of a reference frequency in one period of the divided clock pulse, and a means for counting the number of pulses of the reference frequency in one period of the divided clock pulse. A delay time display device for a BBD, comprising means for displaying the number of pulses.
JP6302783U 1983-04-28 1983-04-28 BBD delay time display device Pending JPS59169134U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6302783U JPS59169134U (en) 1983-04-28 1983-04-28 BBD delay time display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6302783U JPS59169134U (en) 1983-04-28 1983-04-28 BBD delay time display device

Publications (1)

Publication Number Publication Date
JPS59169134U true JPS59169134U (en) 1984-11-12

Family

ID=30193216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6302783U Pending JPS59169134U (en) 1983-04-28 1983-04-28 BBD delay time display device

Country Status (1)

Country Link
JP (1) JPS59169134U (en)

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