JPS60119137U - pulse generator - Google Patents
pulse generatorInfo
- Publication number
- JPS60119137U JPS60119137U JP527684U JP527684U JPS60119137U JP S60119137 U JPS60119137 U JP S60119137U JP 527684 U JP527684 U JP 527684U JP 527684 U JP527684 U JP 527684U JP S60119137 U JPS60119137 U JP S60119137U
- Authority
- JP
- Japan
- Prior art keywords
- output
- latch
- pulse width
- counter
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Pulse Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来技術によるパルス発生器の構成図、第２
図は第１図の各部の信号波形図、第３図は本考案の一実
施例のパルス発生器の構成図である。
４・・・発振器、５・・・ＡＮＤゲー）、６，９・・・
カウンタ、７．１０・・・ラッチ、訃・・セレクタ、１
１・・・デジタル比較器、１２・・・フリップ・フロッ
プ。FIG. 1 is a block diagram of a pulse generator according to the prior art, and FIG.
The figure is a signal waveform diagram of each part of FIG. 1, and FIG. 3 is a block diagram of a pulse generator according to an embodiment of the present invention. 4... Oscillator, 5... AND game), 6, 9...
Counter, 7.10...Latch, Death...Selector, 1
1...Digital comparator, 12...Flip-flop.
Claims (1)
の出力を選択するための値を保持するう” ツチ、選
択された出力をカウントするカウンタの出力を比較出力
させるためのラッチ、該比較出力によりリセ、ツトされ
るフリップ・フロップから成り、パルス幅を指数表示す
る場合の指数部を前述ラッチに、仮数部を後述ラッチに
設定し、仮数部のラッチ出力とカウンタの出力が等しい
時にフリップ・フロップをリセットするようｉこ構成し
、各ラッチにパルス幅の指数部と仮数部を設定すること
によりパルス幅を任意に設定可能にしたことを特徴とす
るパルス発生器。A group of counters that count the output of the oscillator, a latch that holds a value for selecting the output of the counter group, a latch that compares and outputs the output of the counter that counts the selected output, and a reset signal that is reset by the comparison output. When the pulse width is displayed as an index, the exponent part is set to the latch described above, and the mantissa part is set to the latch described later. When the latch output of the mantissa part and the output of the counter are equal, the flip-flop is set. 1. A pulse generator characterized in that the pulse width is configured to be reset, and the pulse width can be arbitrarily set by setting an exponent part and a mantissa part of the pulse width in each latch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP527684U JPS60119137U (en) | 1984-01-20 | 1984-01-20 | pulse generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP527684U JPS60119137U (en) | 1984-01-20 | 1984-01-20 | pulse generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60119137U true JPS60119137U (en) | 1985-08-12 |
Family
ID=30481631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP527684U Pending JPS60119137U (en) | 1984-01-20 | 1984-01-20 | pulse generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60119137U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63189011A (en) * | 1987-02-02 | 1988-08-04 | Nippon Telegr & Teleph Corp <Ntt> | Programmable delay circuit |
-
1984
- 1984-01-20 JP JP527684U patent/JPS60119137U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63189011A (en) * | 1987-02-02 | 1988-08-04 | Nippon Telegr & Teleph Corp <Ntt> | Programmable delay circuit |
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