JPH0247850U

JPH0247850U -

Info

Publication number: JPH0247850U
Application number: JP12641688U
Authority: JP
Priority date: 1988-09-27
Filing date: 1988-09-27
Publication date: 1990-04-03

Description

[Brief explanation of drawings]

第１図は、本考案の第１の実施例を示すブロツ
ク図、第２図は第１図の詳細を示す回路図、第３
図は第２図のタイミング図、第４図は本考案の第
２の実施例を示す回路図である。１……カウンタ、２……バツフア、３……1/2
分周器、４……カウンタ、５……比較器、６……
1/2分周器、２１〜２８……Ｄフリツプフロツプ
、３１〜３７……２入力ＸＯＲゲート、４１……
７入力ＯＲゲート、５１〜５２……２入力ＡＮＤ
ゲート、６１……２入力ＯＲゲート、７１……２
入力ＮＯＲゲート、８１……ＮＯＴゲート、１０
１〜１１６……Ｊ−Ｋフリツプフロツプ。 FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing details of FIG. 1, and FIG.
The figure is a timing diagram of FIG. 2, and FIG. 4 is a circuit diagram showing a second embodiment of the present invention. 1...Counter, 2...Batsuhua, 3...1/2
Frequency divider, 4... Counter, 5... Comparator, 6...
1/2 frequency divider, 21-28...D flip-flop, 31-37...2-input XOR gate, 41...
7 input OR gate, 51~52...2 input AND
Gate, 61...2 input OR gate, 71...2
Input NOR gate, 81...NOT gate, 10
1-116...J-K flip-flop.

Claims

[Scope of utility model registration request]

In the DPLL method, which generates a reception clock synchronized with the reception data from the reception data on the transmission path and the system clock generated independently by the reception station, the system clock is used as the first counter only while the reception data is "0". The buffer to be output and the number of clocks transmitted from the first 1/2 frequency divider after the reset signal goes to "L" level, the count value is cleared to 00, and the reset signal returns to "H" level. A first counter that counts , and its entire output when the reset signal goes to "L" level.
The reset signal returns to the "H" level, and the received data changes from "0" to "1".
In this case, a latch takes in the value of the first counter, outputs and holds the content, and when the reset signal goes to "L" level, the count value is cleared to 00, and the reset signal returns to "H". Then, when the received data changes from "0" to "1", the second counter counts the system clock, and when the count value becomes equal to the content of the latch, the count value is set to 00 and the counting operation is started again. , a comparator that compares the content of the latch and the content of the second counter, and outputs a "L" level if they match; otherwise, outputs an "H"level; and the system clock output from the buffer. The first 1/2 frequency divider divides the frequency of the received clock by 2, and the second 1/2 frequency divider divides the output of the first comparator by 2 and outputs the received clock. Reception clock generation circuit.