JPH0357668U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a block diagram of one embodiment of the horizontal synchronizing signal generating circuit of the present invention, Figs. 2 a to e, and Figs. 3 a to d.
, and FIGS. 4a to 4f are timing charts for explaining the operation of FIG. 1, respectively. 3...N-ary counter, 4...Input side clear pulse generation section, 5...Counting side clear pulse generation section, 6
. . . gate pulse generation section, 7 . . . clear gate section, 10 . . . synchronization signal output section.

Claims (1)

[Claims for Utility Model Registration] An N-ary counter that counts a clock signal of N times the horizontal synchronization frequency whose phase is locked to a color burst signal of a video signal, and outputs N-1 count data at a specified synchronization occurrence timing; a counting-side clear pulse generator that outputs a counting-side clear pulse when the counting data is N-1; and a counting-side clear pulse generator that limits an input horizontal synchronizing signal synchronously separated from the video signal to the pulse width of the clock signal; an input-side clear pulse generation section that outputs a clear pulse; an inhibition gate generation section that outputs an inhibition gate signal during an input-side clear inhibition period of several clocks of the clock signal immediately after the count data reaches N-1; a clear gate section that supplies an OR gate pulse between the counting side clear pulse and the input side clear pulse during the non-output period of the gate signal to clear and reset the counter; and a clear gate section that clears and resets the counter; a synchronization signal output unit that regenerates and outputs an output horizontal synchronization signal that is substantially the same as the input horizontal synchronization signal when the OR gate pulse reaches N-1 and when the OR gate pulse is output before the count data reaches N-1; horizontal synchronization signal generation circuit.