JPH05236295A - Frame synchronization processing circuit for muse signal - Google Patents

Abstract

PURPOSE:To quickly implement frame synchronization at channel changeover. CONSTITUTION:A MUSE signal frame synchronization processing circuit is provided with a gate circuit receiving a pulse (f) outputted by using channel changeover as a trigger signal and an output of a frame pulse detection section 6 or the like, respectively. In the case of channel changeover, an internal frame pulse generating section 7 is reset by using an external frame pulse (a) detected in succession to the pulse (f) and a PLL section 9 is reset and initialized and synchronized with a MUSE signal of a designated channel quickly.

Description

Detailed Description of the Invention

[0001]

The present invention relates to MUSE (multiple sub
-Nyquist sampling encoding) Involved in signal processing circuit,
The present invention relates to frame synchronization and PLL circuit control during channel switching.

[0002]

2. Description of the Related Art In the MUSE system for high-definition broadcasting, a frame synchronizing pulse is superimposed on the first and second two lines of each frame, and the frame pulse is detected from this voltage waveform. On the other hand, a counter for counting one frame is provided inside the device, and a frame pulse is internally generated for each frame to perform frame synchronization of the device. The detection frame pulse is appropriately compared with the internal frame pulse. For example, when the consecutive non-matches are eight times, it is regarded as out of synchronization, and the detection frame pulse resets the counter to return to the synchronization state. Operate. Hereinafter, with reference to FIG. 4, the conventional MUS described above.
An example of the E signal frame synchronization processing circuit will be described. FIG. 4B is a voltage waveform of a pulse for frame synchronization superimposed on the first and second two lines of each frame of the MUSU signal, and the point shown on the second line is called a frame pulse point. It is used as a reference point for frame synchronization.
In FIG. 4, (A), 6 is a frame pulse detector,
The correlation between the two lines and the correlation between four consecutive clocks are obtained, and the frame pulse point is detected based on the result,
The external frame pulse a is output. Reference numeral 7 denotes an internal frame pulse generator composed of a counter, which counts the cycle of one frame (480 CK × 1125 lines, CK: 16.2 MHz) and outputs an internal frame pulse b for each frame. 8 is an external frame pulse a and an internal frame pulse b
A comparator composed of a 3-bit counter or the like for comparing the timings with, 9 is a PLL part for horizontal phase synchronization for outputting a required clock pulse such as a resample clock, and 10 is a PLL part 9 for counting 4 frame periods. A counter that outputs a reset pulse. Now, when the external frame pulse a and the internal frame pulse b do not match eight times in succession, the comparator 8 uses the external frame pulse a as a reset signal for the internal frame pulse generator 7, the PLL unit 9 and the counter 10.
Output to. Therefore, at the newly detected frame pulse point, the internal frame pulse generation unit 7 starts counting one frame, the PLL unit 9 is also initialized at the same time, the loop filter coefficient is set to the wide band mode, and the synchronization pull-in operation is started. After four frames, the counter 10 outputs a reset signal, the loop filter coefficient of the PLL unit 9 is reset to the narrow band mode, and the perfect synchronization state is entered. As described above, it takes 12 frames to completely enter the synchronization state after the synchronization is lost.

Now, when performing a channel switching operation for a plurality of high-definition programs, MUSs having different synchronization relationships from each other.
According to the above sequence of frame pulse detection, even though it is an E signal, the first 8 frames continue to compare the external and internal frame pulses as an uncertain signal due to noise, etc., and then the input frame pulse. Depending on the point, the synchronization pull-in operation starts. Therefore, even in the case of channel switching, it takes 12 frames to completely enter the synchronization state.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and immediately resets the internal frame pulse generation section and the PLL section at the next external detection frame pulse point at the time of channel switching. The present invention provides a frame synchronization processing circuit which is initialized by the above process and is quickly synchronized with the MUSE signal of the designated channel.

[0005]

In order to solve the above-mentioned problems, the present invention provides a frame pulse detector for detecting a frame pulse point from a MUSE signal and an internal frame pulse for each frame by counting one frame period. An internal frame pulse generation section for generating, a counter for comparing the frame pulse from the frame pulse detection section with a pulse from the internal frame pulse generation section, and a signal for continuously outputting a signal when they do not match a predetermined number of times, and the counter. And a horizontal phase synchronization PLL unit for outputting a required clock pulse such as a resample clock.
In a signal frame synchronization processing circuit, a pulse generator that generates a predetermined pulse by using a channel switching signal as a trigger, and a gate that receives an output of the pulse generator, an output of the counter, and an output of the frame pulse detector, respectively. And a circuit for resetting the internal frame pulse generator by the output pulse of the frame pulse detector based on the output signal from the pulse generator or the counter and initializing the PLL unit. A signal frame synchronization processing circuit is provided.

[0006]

With the above construction, the MU according to the present invention
The frame synchronization processing circuit of the SE signal is provided with a gate circuit which receives the output of the pulse generation unit triggered by channel switching and the output of the frame pulse detection unit, etc. On the basis of the output, the output pulse of the frame pulse detection unit detected next resets the internal frame pulse generation unit and resets and initializes the PLL unit, and quickly synchronizes with the MUSE signal of the designated channel.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The MUSE according to the present invention will be described below with reference to the drawings
An embodiment of the signal frame synchronization processing circuit will be described in detail. FIG. 1 is a block diagram of an essential part showing an embodiment of a frame synchronization processing circuit for a MUSE signal according to the present invention, and FIG. 2 is a time chart showing the operation of this circuit. In addition, in FIG.
The same parts as those in FIG. In FIG. 1, reference numeral 1 is a gate that receives an external frame pulse a and an internal frame pulse b, and outputs a pulse to the output c when the input pulses a and b match. 2 is a 3-bit counter, the internal frame pulse b is connected to the clock input terminal, the output c of the gate 1 is connected to the reset terminal,
When there is no reset pulse from the output c, the output signal e becomes "H" level by counting up with the internal frame pulse b eight times. 3 is a pulse generation circuit, which is based on a switching signal d input in response to a channel switching operation,
A pulse f having a time width of at least one frame period is output. An OR gate 4 receives the signal e and the pulse f, and outputs one of the input signals to the output g. That is, the output g outputs either the signal e when the external frame pulse a and the internal frame pulse b do not match eight times in a row, or the pulse f during the channel switching operation. The gate 5, which receives the output g and the external frame pulse a,
When the output g is at the "H" level, that is, the signal e or the pulse f, the external frame pulse a is output, and the internal frame pulse generator 7, the 2-bit counter 10 and the PLL
Each of the parts 9 is reset.

Next, the operation of the MUSE signal frame synchronization processing circuit according to the present invention will be described with reference to FIG.
First, in the steady operation state, the external frame pulse a
And the internal frame pulse b are in a synchronous relationship, and the gate 1
The output c of the above outputs a reset pulse for each frame to reset the 3-bit counter 2, and if there is no channel switching operation, as a result, no reset pulse is output to the output h of the gate 5. Therefore, the synchronization by the internal frame pulse b, that is, the steady operation is continued. Next, when the channel switching operation is performed, the switching signal d is input to the pulse generation circuit 3 and the pulse f is output. As a result, the pulse f is output to the output g of the OR gate 4, the next external frame pulse a is output to the output h of the gate 5, and the internal frame pulse generator 7 and the 2-bit counter 10 are output.
And the PLL unit 9 are reset. That is, the synchronization operation based on the external frame pulse point from the MUSE signal of the designated channel is started. Next, when the synchronization is lost, the output e of the 3-bit counter 2 is at the "H" level due to the non-coincidence of the external frame pulse a and the internal frame pulse b eight times in succession. Level, the next external frame pulse a is output to the output h of the gate 5, resets the internal frame pulse generation unit 7, the 2-bit counter 10 and the PLL unit 9, respectively, and synchronizes based on the external frame pulse point. Return to.

FIG. 3 is a block diagram of the essential parts showing another embodiment of the frame synchronization processing circuit for MUSE signals according to the present invention. When a dedicated LSI in which frame synchronization processing blocks such as a frame pulse detection unit, an internal frame pulse generation unit, and a counter are integrated is used, the clock for driving the dedicated LSI is changed to a high-speed clock during the channel switching operation. By switching, the time required to synchronize with the MUSE signal of the designated channel can be shortened. In the figure, 11 is a pulse generation circuit that generates a predetermined pulse according to a channel switching signal, 12 is a clock switching circuit that switches between two types of clock 1 and clock 2, and 13 is L
It is SI. Now, the frequency of the clock (clock 1) in the steady operation is set to, for example, 16.2 MHz, and the frequency of the speeded up clock (clock 2) is increased by, for example, 6 times 97.2.
The pulse width from the pulse generation circuit 11 is set to 8/6 frame period. At the time of channel switching operation, if the pulse switching circuit is driven by the pulse from the pulse generation circuit 11 to switch the clock 1 to the clock 2, about 1/6 of the time is required as compared with the case of the conventional circuit. It is possible to start the synchronization pull-in operation based on the external frame pulse point detected from the MUSE signal of the designated channel in time.

[0010]

As described above, the M according to the present invention is
In the USE signal frame synchronization processing circuit, at the time of channel switching, the internal frame pulse generation unit is reset by the externally input frame pulse that is input next and the PLL unit is reset and initialized to the MUSE signal of the designated channel. I tried to synchronize. Therefore, the time required for synchronization can be significantly reduced. Also,
When the frame synchronization processing block is an LSI, the time required for synchronization can be shortened by speeding up the clock that drives the LSI.

[Brief description of drawings]

FIG. 1 is a principal block diagram showing an embodiment of a frame synchronization processing circuit for a MUSE signal according to the present invention.

FIG. 2 is a time chart for explaining the operation of the frame synchronization processing circuit of the MUSE signal according to the present invention.

FIG. 3 is a block diagram of an essential part showing another embodiment of the frame synchronization processing circuit of the MUSE signal according to the present invention.

FIG. 4A is a block diagram of essential parts showing an embodiment of a conventional frame synchronization processing circuit for MUSE signals, and FIG. 4B is an MU.
7 is a time chart of a voltage waveform of a frame pulse for vertical synchronization superimposed on an SE signal.

[Explanation of symbols]

 1 gate 2 3 bit counter 3 pulse generation unit 4 OR gate 5 gate 6 frame pulse detection unit 7 internal frame pulse generation unit 8 3 bit counter 9 PLL unit 10 2 bit counter 11 pulse generation circuit 12 clock switching circuit 13 LSI

Claims (2)

[Claims] 1. A frame pulse detector for detecting a frame pulse point from a MUSE signal, an internal frame pulse generator for counting one frame period to generate an internal frame pulse for each frame, and the frame pulse detector. Of the internal frame pulse generator and the counter that outputs a signal when they do not match a predetermined number of times in succession, and a clock pulse that is controlled by the output of the counter and that requires a resample clock or the like. MUS consisting of output PLL for horizontal phase synchronization
In the frame synchronization processing circuit of the E signal, a pulse generation unit that generates a predetermined pulse by using a channel switching signal as a trigger, an output of the pulse generation unit, an output of the counter, and an output of the frame pulse detection unit are respectively input. A gate circuit is provided, and the internal frame pulse generator is reset by the output pulse of the frame pulse detector based on the output signal from the pulse generator or the counter, and the PLL unit is initialized. A frame synchronization processing circuit for a MUSE signal. 2. A frame synchronization processing circuit for a MUSE signal using a dedicated LSI integrating the frame pulse detection unit, internal frame pulse generation unit, counter, etc., and generates a predetermined pulse using a signal by channel switching operation as a trigger. And a clock switching circuit for switching the clock pulse for driving the LSI by the pulse from the pulse generating circuit, and the clock for driving the LSI is set to a high-speed clock by the clock switching circuit. Switching, M when switching channels
A frame synchronization processing circuit for a MUSE signal, characterized in that the time required to synchronize with the USE signal is shortened.