JPH0591096A - Clock recovery circuit - Google Patents

Abstract

PURPOSE:To realize the clock recovery circuit not using a clock with a high frequency. CONSTITUTION:A reference data clock from a reference data clock generating section 7 is divided into N by a delay section 8, each divided clock is delayed and N sets of clock signals with a different phase are generated. A selection section 9 selects a clock signal with a least phase difference from that of the digital data among the said N sets of clock signals based on an average lead or lag signal from a sequential filter 2 and outputs the selected signal as a data clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit, and more particularly to a clock recovery circuit having a frequency equal to that of a data clock.
The present invention relates to a clock regenerator circuit that is divided and delayed (phase difference) and is used as a data clock to reduce circuit component cost and power consumption.

[0002]

2. Description of the Related Art In order to detect demodulated digital data in a receiver, a data clock which is a timing signal phase-synchronized with the digital data is required. An external timing method and a self-timing method are known for this data clock recovery (clock recovery). The external timing method is a method of transmitting a timing signal on another channel in addition to the digital data signal. The method is a method of extracting a timing signal from a signal sequence of transmitted digital data.

The present invention aims to improve the self-timing method among the above-mentioned timing methods. A block diagram of a conventional clock recovery circuit based on such a method is shown in FIG. In the figure, 1 is a binary phase comparison unit, 2 is a sequential filter, 3 is a threshold setting unit, 4 is a phase control unit, 5 is a clock frequency dividing unit, and 6 is a clock generating unit. The circuit of FIG. 5 is generally well known as a binary quantized digital PLL (phase locked loop). This circuit has a configuration in which a clock N times the data clock frequency is prepared, the clock (data clock) divided by N is compared with the phase of the received signal, and PLL control is performed so that they match. Is becoming The operation of each unit will be described below.

First, the clock generator 6 generates a clock that is N times the data clock. Clock divider 5
Is based on the information from the phase controller 4
The clock generated from is divided by N to generate a data clock. The phase accuracy of the data clock is determined by this frequency division ratio, and if N = 32, for example, 1/32 of the bit interval
Phase accuracy.

The binary phase comparator 1 compares the phase with the data clock at the change point of the demodulated digital data and outputs the advance pulse a or the delay pulse b as shown in FIG.

The sequential filter 2 performs time averaging of the leading pulse a or the lagging pulse b. For example, if a random walk filter is used as the sequential filter, when the leading pulse a is input, the up / down counter that constitutes the random walk filter is counted up, and conversely, when the delayed pulse b is input, the count down is performed. Counter is threshold setting unit 3
When the pulse count number set in 1 is reached, overflow or underflow occurs, and the time-averaged leading pulse c or the time-averaged delayed pulse d is output and the counter is reset. For example, as shown in FIG. 6, if the pulse count number is set to 8 in the threshold setting unit 3, the sequential filter outputs a time-averaged leading pulse c when the cumulative number of leading pulses a is 8 and delays When the cumulative number of pulses b reaches 8, the time-averaged delayed pulse d is output.

The phase controller 4 controls the clock frequency divider 5 based on the information from the sequential filter 2. Specifically, when the time-averaged advance pulse c is input, the frequency division ratio of the frequency division unit 5 is controlled to be N−1, and the time-averaged delay pulse d is input. And the frequency division ratio is controlled to be N + 1, and the data clock N
The phase is delayed or advanced with respect to the double clock. As a result, the digital data and the reproduced data clock can be phase-synchronized with an accuracy of 1 / N of the 1-bit interval.

[0008]

However, this conventional method
The problem is in high-speed digital data
When the data clock is regenerated by, for example, 10 Mb
For digital data of ps, clock generator 6
If the clock frequency generated from N = 32, then 10 × 10⁶X32 = 320x10⁶  320MHz more, use a fairly high frequency
That will be the case. Generally, such high frequencies
If a circuit that operates with a number is composed of digital circuits,
Road component costs will increase and power consumption will increase.
It

An object of the present invention is to reduce the component cost and power consumption by enabling the clock recovery circuit to be constructed without using a high clock frequency.

[0010]

In order to achieve the above object, a clock recovery circuit of the present invention inputs demodulated digital data and a data clock signal and compares their phases to obtain at least a lead signal or a delay signal. A phase comparison unit that outputs a signal, the lead signal and the delay signal are input, time averaging of the signals is performed, and time averaging means that outputs at least an averaging lead signal or an averaging delay signal, and the data A reference data clock generator that generates a reference data clock having the same frequency as the clock signal,
Based on the averaging advance signal or the averaging delay signal, the N clock signals based on the averaging advance signal or the averaging delay signal Among them, a selection unit that selects a clock signal having the smallest phase difference from the digital data and outputs the selected clock signal as the data clock signal is summarized.

[0011]

The reference data clock having the same frequency as that of the data clock signal is divided into N clock signals having different phases in the delay unit, and the phase difference with the digital data is maximized based on the averaged advance or delay signal in the selection unit. A small clock signal is selected and output as a digital data clock signal.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention shown in the drawings will be described below. In FIG. 1, the same reference numerals as those in FIG. 4 represent the same or similar circuits. In particular, as a configuration different from that of FIG.
Instead of this, a selection unit 9, a delay unit 8 and a reference data clock generation unit 7 are used as shown in the figure. The present invention does not require a clock having a frequency as high as N times the data clock in the conventional example, and can be easily realized with a clock equivalent to the data clock.

Since the binary phase comparator 1, the sequential filter 2, and the threshold setting unit 3 have the same configuration and operation as in the conventional example, the reference data clock generating unit 7, the delay unit 8 and the selecting unit 9 will be operated hereinafter. And the circuit will be described. In the following, for example, (1) such as DL (1) means a subscript representing a different DL.

First, the reference data clock generator 7 generates a reference data clock having the same frequency as the data clock, and the delay unit 8 has N-1 delay circuits DL (1) to DL as shown in FIG. Data clock M (m) (m = 0, which is composed of (N-1) and has different phases (delay times) divided by N with respect to each reference data clock.
, 1, 2, 3, ..., N-1) are output. Here, if the cycle of 1 bit of data is D, N = 32, each delay time n (m) with respect to the reference data clock (m = 1, 2,
3, ..., N-1) is n (m) = m * D / N (m = 1,2,3, ..., N-1) = m * D / 32 (m = 1,2,3,) ..., 31). Here, m = 0 (n (m) =
0) is a reference data clock. FIG. 3 shows the above-described 32 divided data clocks with different phases. The reference data clock M (0) is delayed by 1 × D / 32, and the reference data clock M (1). A data clock M (2) delayed by 2 × D / 32 with respect to (0), a data clock M (3) delayed by 3 × D / 32 with respect to the reference data clock n (0),
......, 31 × D / with respect to the reference data clock M (0)
The data clock M (31) delayed by 32 is shown.

The selection unit 9 divides the data clock M (m) (m = 0) with different phases (delay time) into N divisions based on the time-averaged advance pulse c or delay lag pulse d output from the sequential filter. , 1, 2, 3, ..., N-
1) are sequentially selected, and control is performed so that the data clock having the smallest phase difference with respect to digital data is selected. For example, when the time-averaged leading pulses c are continuously input, the selection unit outputs N divided data clocks having different phases to M (0), M (1), M (2), M.
(3), ... Are sequentially selected to control the delay of the phase of the data clock with respect to the digital data, and conversely, when the time-averaged delayed pulse d is continuously input, the selection unit outputs N The divided data clocks having different phases are M (0), M (N-1), M (N-2), M (N-).
3), ..., Are sequentially selected, and control is performed to advance the phase of the data clock with respect to the digital data. As a result, the digital data and the data clock can be phase-synchronized with an accuracy of 1 / N of the 1-bit data interval.

[0016]

As described above, according to the present invention, a clock recovery circuit can be realized without using a clock having a higher frequency than in the conventional example, so that the cost and power consumption of the circuit can be reduced. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clock recovery circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a delay unit 8.

FIG. 3 is a timing chart showing data clocks divided into 32 and having different phases.

FIG. 4 is a block diagram showing a conventional clock recovery circuit.

5 is a timing chart for explaining the operation of the clock recovery circuit of FIG.

6 is a timing chart for explaining the operation of the clock recovery circuit of FIG.

[Explanation of Codes] 1 Binary phase comparison unit 2 Sequential filter 3 Threshold setting unit 7 Reference data clock generation unit 8 Delay unit 9 Selection unit

Claims (1)

[Claims] 1. A phase comparator for inputting demodulated digital data and a data clock signal, performing phase comparison between them, and outputting at least a lead signal or a lag signal; and inputting the lead signal and the lag signal. A time averaging means for performing time averaging of these signals and outputting at least an averaging advance signal or an averaging delay signal; and a reference data clock generator for generating a reference data clock having the same frequency as the data clock signal. A delay unit which is supplied with the reference data clock and generates N clock signals having different phases divided into N with respect to the clock; and the N clocks based on the averaging advance signal or the averaging delay signal. Select the clock signal with the smallest phase difference from the digital data among the signals and output it as the data clock signal. Clock recovery circuit characterized by comprising a selection unit.