JP2807337B2 - Drive circuit for CCD image sensor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a CCD image sensor driving circuit that controls a read operation of an image signal in a CCD image sensor.

(Prior Art) Reading of an image signal and processing of the read image signal in a CCD image sensor are performed based on various clock signals. As a drive signal generation circuit for generating such various clock signals, there is, for example, one configured as shown in FIG.

In FIG. 3, the drive signal generation circuit includes a plurality of cascade-connected frequency dividers 1 to 5 and a decoding circuit 6 for decoding outputs of these frequency dividers.

In such a configuration, the master clock signal serving as a reference clock signal are sequentially divided by the frequency divider 1-3, to obtain a clock signal 2f _H as the divided output of the frequency divider 3. Further, the clock signal with the clock signal is divided by the frequency divider 4 f _v is generated, a horizontal period signal f _H which is divided by the frequency divider 5 to set the horizontal period of the CCD image sensor Is generated.

The clock signal generated by each of the frequency dividers 1 to 5 is applied to a decoding circuit 6 and decoded,
Various clock signals necessary for driving the D image sensor are generated.

In such a circuit configuration, an image output signal from the respective clock signals and the CCD image sensor of the three frequency dividers 1-3 to generate successively dividing the clock signal 2f _H from the master clock signal and the horizontal driving pulse signal The output waveform of the reset gate drive pulse signal has a timing relationship as shown in FIG.

In FIG. 4, the image output signal has a unit period of three periods including a reset period for resetting the image signal of the CCD charge detection unit, a feed-through period of the reset reference level, and a signal period for extracting the image signal. . In such an image output signal, output signals in the feedthrough period and the signal period are sampled and held, respectively, and CDS signal processing is performed by comparing the sampled and held signals, thereby performing image processing.

For the image output signal subjected to such image processing, the change point 7 of each of the divided clock signals in the frequency dividers 1 to 3 in the conventional circuit configuration has the timing shown in FIG. Was. That is, each divided clock signal is not synchronized with the drive signal of the CCD image sensor. Further, a phase shift occurs due to a change in the operating temperature of the drive circuit, and the phase shift of the frequency-divided clock signal of the frequency divider 3 having a large delay time with respect to the master clock signal is particularly large.

As described above, the frequency-divided clock signals in the frequency dividers 1 to 3 are not synchronized with the drive signal of the CCD image sensor and have a phase shift.
As shown in the figure, each frequency-divided clock signal sometimes has a change point in a feedthrough period or a signal period of an image output signal.

Therefore, frequency-divided noise 8 due to a change in the frequency-divided clock signal is generated in the image output signal in the feed-through period and the signal period used for image processing as shown in FIG. 4, or the image output signal is sampled. Frequency noise may be mixed in the clock signal for this purpose.

Therefore, if image processing is performed in a state where noise is included in the image output signal, it is difficult to obtain a normal image. For example, when the CCD image sensor has high sensitivity, as shown in FIG. There has been a problem that fixed noise 9 having vertical stripes appears in the image, and a normal image cannot be obtained.

(Problems to be Solved by the Invention) As described above, in the conventional CCD image sensor driving circuit, when the frequency-divided output signals of a plurality of frequency dividers for generating the horizontal period signal change. The frequency division noise generated in the image output signal was mixed in the image output signal. For this reason,
Fixed pattern noise is generated in an image obtained by performing image processing on an image output signal, which causes image deterioration.

Therefore, the present invention has been made in view of the above, and an object of the present invention is to suppress the influence of frequency-divided noise generated when a horizontal periodic signal is generated on an image output signal by using a simple configuration. It is another object of the present invention to provide a CCD image sensor driving circuit capable of preventing image deterioration.

[Constitution of the Invention] (Means for Solving the Problems) In order to achieve the above-described object, the present invention provides a frequency dividing process which generates a horizontal periodic signal for controlling horizontal driving of a CCD image sensor from a main clock signal. And a signal generating means for generating a horizontal periodic signal from the main clock signal by including the changing points of the plurality of pulse signals in the reset period of the image output signal.

(Operation) In the above configuration, according to the present invention, a plurality of pulse signals generated in a process of generating a horizontal periodic signal are changed within a reset period of an image output signal, and an image output of synchronous noise caused by the change of the pulse signal is output. The mixing into the signal is prevented.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a main configuration of a CCD image sensor driving circuit according to an embodiment of the present invention.

In FIG. 1, a driving circuit includes synchronous counter circuits 11, 12, 13, and 1 as main components for generating various driving clock signals for driving a CCD image sensor.
5. An asynchronous counter circuit 14 and a decode circuit 16 are provided.

Three synchronous counter circuits 11, 12, and 13 and an asynchronous counter circuit 14 are cascaded, and the first-stage counter circuit 11 receives a master clock signal as a main clock signal among the drive signals of the CCD image sensor. The counter circuits 12, 13, and 14 at the next and subsequent stages receive the output of the counter circuit at the previous stage as an input.

Among these counter circuits 11 to 14, the master clock signal is given to the synchronous counter circuits 11 to 13, and the counter circuits 11 to 13 divide the respective input clock signals in synchronization with the master clock signal. And a counter circuit
To obtain a divided clock signal 2f _H as an output of 13. Divided clock signal obtained by these counter circuits 11 to 13 is applied to a decoder circuit 16, the divided clock signal 2f _H is given to the counter circuit 14 and the synchronous counter circuit 15 asynchronous.

The asynchronous counter circuit 14 is a synchronous counter circuit.
In response to the divided clock signals 13, it divides the divided clock signal, and generates a vertical cycle signal f _v that determines the vertical period. This vertical cycle signal is applied to the decoder circuit 16.

Synchronous counter circuit 15 receives the divided clock signal of the counter circuit 13, the divided clock signal to 1/2 frequency-divides in synchronization with the master clock signal, determining a horizontal period f _H
Are generated. That is, the horizontal period signals are cascade-connected, and synchronous counter circuits 11, 12, 13, 15 for performing frequency division processing in synchronization with the master clock signal.
Has been generated by F _H generated in this way
Are supplied to the decoder circuit 16.

The decoder circuit 16 decodes the frequency-divided clock signals of the respective counter circuits 11 to 15 and generates various clock signals necessary for driving the CCD image sensor.

In such a configuration, when the horizontal period signal is generated from the master clock signal, the synchronous counter circuits 11 to
As shown in FIG. 2, the change point 17 of each divided clock signal generated as the output of 13 is adjusted by appropriately adjusting the phase of the master clock signal serving as the synchronization signal of each of the counter circuits 11 to 13 as shown in FIG. Each divided clock signal is generated so as to be within the reset period of the image output signal. That is, as shown in FIG.
Each frequency-divided clock signal is changed within the high-level state of the reset gate drive pulse signal. This can be achieved by manipulating the phase of the master clock signal because each of the counter circuits 11 to 13 generates the divided clock signal in synchronization with the master clock signal. Can be prevented, and all the transition points 17 of each divided clock signal can be reliably set within the reset period of the image output signal.

As a result, frequency-divided noise that affects the horizontal drive of the CCD image sensor due to a change in each frequency-divided clock signal is concentrated in the reset period of the image output signal.
Since the reset period is a period in which the image output signal is forcibly fixed to a predetermined level, the influence on the frequency division noise can be reduced. Further, it is possible to prevent the frequency division noise from being mixed into the image output signal in the period required for the image processing described above. That is, it is possible to completely remove the synchronizing noise generated when the horizontal periodic signal required for driving the CCD image sensor is generated from the signal portion of the image output signal.

As a result, a high-quality image output signal that does not include synchronization noise is obtained.
It is possible to obtain a good image that does not include fixed pattern noise as shown in the figure.

The present invention is not limited to the above embodiments, for example, in the above embodiment is obtained a frequency-divided clock signal f _H by the counter circuit 11～13,15 of three stages connected in cascade, The number of stages is not particularly limited. In addition, a counter circuit that generates a divided clock signal including a change point that becomes frequency division noise can set the change point of the generated divided clock signal within the reset period of the image output signal.
The counter may be an asynchronous counter instead of a synchronous counter.

[Effects of the Invention] As described above, according to the present invention, the change points of the plurality of pulse signals generated in the process of dividing the main clock signal to generate the horizontal periodic signal are determined by the reset period of the image output signal. Since it is set to within, the synchronizing noise attributed to the change in the pulse signal can be removed from the signal portion required for image processing in the image output signal.

As a result, it is possible to provide a drive circuit for a CCD image sensor that can obtain a good image in which fixed pattern noise does not appear from an image output signal that does not include synchronous noise.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a driving circuit for a CCD image sensor according to the present invention. FIG. 2 is an operation timing chart of the circuit shown in FIG. 1. FIG. FIG. 4 is a block diagram showing a configuration example of a drive circuit. FIG. 4 is an operation timing chart of the circuit shown in FIG. 3. FIG. 5 is a diagram showing a noise pattern of an image obtained by being driven by the drive circuit shown in FIG. is there. 1-5 Divider 6,16 Decoder circuit 7,17 Change point of divided clock signal 8,18 Divided noise 9 Fixed pattern noise 11-13,15 Synchronous Counter circuit 14 …… Asynchronous counter circuit

Claims (1)

(57) [Claims] A main clock includes a plurality of pulse signal change points generated in a frequency dividing process for generating a horizontal period signal for controlling a horizontal drive of a CCD image sensor from a main clock signal within a reset period of an image output signal. A driving circuit for a CCD image sensor, comprising: signal generation means for generating a horizontal periodic signal from a signal.