JP3024130B2 - Arbitrary phase extraction circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character display semiconductor integrated circuit for generating auxiliary characters and patterns in an apparatus for displaying an image on a CRT such as a TV or VTR.

2. Description of the Related Art In recent years, in the field of one-chip microcomputers (microcomputers), a variety of types having a built-in character display function for TVs and VTRs have been increasing. This type of semiconductor integrated circuit device generally includes an oscillation terminal for an oscillation circuit mainly using a crystal oscillator used as a system clock for operating a microcomputer, and a clock used for operation of a character display circuit and position detection on a screen. It has an oscillation terminal for the LC and CR oscillation circuits. This is because an image display clock requires a fast oscillation rise of 1 μsec or less and a signal that is phase-synchronized on the order of several nsec. This is because an element requiring several msec cannot be used. That is, the image display clock stops oscillating at every horizontal synchronizing signal (HSYNC) input at an interval of 63.5 μsec, and oscillates quickly and stably at the last edge of the synchronizing signal, thereby realizing accurate phase synchronization and realizing the screen synchronization. This is because the image is not shaken due to a position shift or a frequency change at the time of rising. Therefore, in a conventional one-chip microcomputer with a built-in character display function, a clock oscillation circuit for image display is realized by a CR oscillation circuit, an LC oscillation circuit, or the like, and has a plurality of oscillation circuits.

However, the above conventional method has a plurality of oscillation circuits, and the number of functional terminals is smaller than the determined number of terminals of the package. Inevitably, there is a problem that not only the cost is increased but also extra terminals are produced and waste is increased.

The present invention has been made to solve the above problems, and provides a semiconductor integrated circuit capable of extracting a signal phase-synchronized with a reference signal such as a horizontal synchronization signal based on an input system clock oscillation output. The purpose is to:

Means for Solving the Problems In order to solve this problem, the present invention generates signals of various phases at the same frequency by delaying an oscillation output signal for a system clock by using a multi-stage delay circuit unit. In order to achieve the above object by identifying the most appropriate signal from these, in summary, a delay circuit for an input signal, a storage circuit held at the timing of the input signal, and the storage circuit A logical sum circuit that combines unit circuits composed of at least one AND circuit that determines the state of the input signal with the timing of the input signal into a plurality of stages, and adds signals from the AND circuits of the unit circuits in each of the stages. Is an arbitrary position extraction circuit provided with

According to the present invention, an input signal can be taken out at a phase synchronized with a clock input signal, so that an occupied oscillation circuit unit is not required, and the number of output terminals and noise can be reduced.

Embodiment Hereinafter, an embodiment of a semiconductor integrated circuit according to the present invention will be described with reference to the drawings.

In this embodiment, the input signal of the delay circuit is a rectangular wave having a duty of about 50% by shaping or dividing a signal oscillated by two terminals using a crystal or ceramic vibrator into a rectangular wave. .

FIG. 1 is a unit circuit B showing a main part of the present invention, which includes a delay circuit composed of inverters B1 and B2 that receive an input signal B12 and output an output signal B18, and a delay time T of the delay circuit.
Inverters B3 and B5, Inverter B to obtain in-phase and out-of-phase signals of input signal B12 without affecting d
3 output B4 as input signal, forward output B8, inverted output B
9, the input is read when the clock signal B15 is at a high level, and stored when the clock signal B15 is at a low level.
A logical product (AND) circuit B10 having the above-mentioned non-inverting output B8, inverting input B4, and input signal B13 as inputs and an output of B17, and the above-described inverting output B9, in-phase input B6, and input signal B14 as inputs, and B16
And an AND circuit B11 that outputs the same.

FIG. 2 shows a configuration in which unit circuits A, B and C equivalent to FIG. 1 are connected. Fig. 1 In practical use, the delay time obtained by adding the minimum delay time determined by the manufacturing process variation of the signal delay time of the inverters B1 and B2 by the number of connection unit circuits is larger than 1/2 of the signal period of the input signal B12. It is necessary to connect a certain number of stages.

Here, a case where the delay signals in the three unit circuits A, B, and C have an appropriate delay will be described as an example. This is because, when the unit circuits are connected under the above-described conditions, one or more unit circuits having an appropriate delay always exist, and can be considered as a representative of the entire operation description.

The unit circuits are connected by connecting signal terminals 18 and 12, 9 and 13, 8 and 14 in the previous and next stages. The outputs 16 and 17 of each stage are input to a logical sum (OR) gate 1. The outputs 16, 17 of all the unit circuits A, B, C except the start and end of the connected unit circuit are input to the OR gate or a group of gates having the same logic by a plurality of gates. The output 2 of the OR gate 1 is the output of the first-stage input signal synchronized in phase with the clock signal 15.

FIG. 3 is a time chart showing the operation of the circuit shown in FIG. 2, and each signal corresponds to each signal shown in FIG. Here, the input terminal A1 of the unit circuit A to which the input synchronization signal of the unit circuit at the preceding stage of the unit circuit A of FIG.
Assuming that 4 changes as indicated by A14 in FIG.
The operation of the circuit of FIG. 2 was shown.

 Hereinafter, a specific operation of the present embodiment will be described.

When the clock input signal A15 is input, the unit circuits A, B, C
Among them, the non-inverted output of the unit circuit whose high level is input to the data latch becomes high level, and the inverted output becomes low level. When the clock input signal A15 shown in FIG. 3 is input, the normal output A8 of the unit circuit A and the normal output B8 of the unit circuit B become high level. The output A16 of the unit circuit A does not output the in-phase signal of the input signal A12 because the input A14 of the non-inverting output from the previous stage and the inverted output A9 of the own stage data latch are at low level. Also, the output A17 of the unit circuit A
Is an input signal A13 having a polarity opposite to that of the input signal A14, and a forward output A8.
Since both are at the high level, they output a signal opposite in phase to the input signal A12.

Similarly, for the other unit circuits B and C, the outputs 16 and 17 of the respective unit circuits are changed to B16 and B17 and B16 and B17 in FIG. 3 according to the state of the normal output and inverted output of the preceding data latch.
Determined as C16, C17.

In other words, when the signals from the respective delay circuits have the same polarity in the previous stage and the own stage, the output of the delay input signal of each stage is prohibited from the outputs 16 and 17, and in the case of the opposite polarity, that is, the delay input signal is
Output is possible only at a changing point when a clock input signal is input. Therefore, when a clock input signal is input, a delay input signal that changes exactly is always output, and an input signal synchronized with the clock input signal is obtained. At this time, the output 2 outputs a signal in phase with the delayed input signal A12, that is, an in-phase signal of the delayed input signal C12, and becomes a signal delayed by one unit circuit with respect to the delayed input signal B12 at the transition point. , And Terr errors, but if the delay amount of the inverter of the unit circuit is selected so as to be a sufficiently small error within a practical range, no problem occurs.

When the duty of the clock input signal is large, the output of the data latch changes according to the delayed input signal during the input of the clock signal, but after the output 2 of the OR gate,
The output may be taken out in synchronization with the clock signal.

Advantageous Effects of the Invention As described above, according to the present invention, an input signal can be extracted with a phase synchronized with a clock input signal. Therefore, when used in an oscillation circuit or the like, another asynchronous clock signal can be generated. It is possible to reduce the number of oscillation circuits that have been separately attached to the conventional semiconductor integrated circuit, thereby effectively using the limited output pins of the semiconductor integrated circuit device and reducing interference from other oscillation terminals. A circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of a semiconductor integrated circuit of the present invention,
FIG. 2 is a circuit configuration diagram showing a part of a circuit in the embodiment of the present invention, and FIG. 3 is a time chart thereof. 1 ... OR gate, 2 ... Output terminal, B1, B2, B3, B5 ... Inverter, B7 ... Data latch, B10, B11 ... AND circuit.

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 5/24 H03K 5/00 H04N 5/06 H04N 5/445

Claims (1)

(57) [Claims] An arbitrary circuit extraction circuit for connecting a unit circuit to a plurality of stages and for calculating and outputting a logical sum of a first output signal and a second output signal output from the unit circuit, comprising: A delay circuit that is delayed by a fixed time and is used as an input signal of the next unit circuit; an inversion signal of the input signal is stored at a clock timing; a non-inversion signal is output as a non-inversion output; A data latch circuit, a first AND circuit for calculating a logical product of an inverted output of the preceding unit circuit, the normal output, and an inverted signal of the input signal, and outputting the result as a first output signal; And a unit circuit having a second AND circuit for calculating a logical product of the non-inverted output, the inverted output, and the input signal and outputting the result as a second output signal.