JPH07101224B2 - Frequency comparison circuit - Google Patents

Description

The present invention relates to a frequency comparison circuit having a frequency hysteresis characteristic.

[Conventional technology]

Conventionally, in various electronic devices, there are cases where two or more frequencies are compared to detect a deviation or a frequency between the two. For example, video tape recorder playback modes (βII, βII
In the switching of I), since the frequencies of both modes are different, the reference mode and the frequency of each mode are compared and the reproduction mode is switched.

In the video tape recorder, for example, the frequency comparison circuit shown in FIG. 5 is used for mode switching.
This frequency comparison circuit comprises frequency division stages 2, 4, 6 and a flip-flop circuit 8. An input signal of frequency f _G from a frequency generator (not shown) is a frequency division input C of frequency division stage 2. The input signal of frequency f _L is the reset input R of the frequency dividing stage 2 and the frequency dividing input of the frequency dividing stage 6.

The output of the frequency dividing stage 4 is the data input D of the flip-flop circuit 8, and the output of the frequency dividing stage 6 is the flip-flop circuit 8.
Of the frequency division stage 6 is taken in according to the frequency division output of the frequency division stage 6, and this is taken out from the output terminal 10 as a frequency comparison output.

In such a frequency comparison circuit, the frequency f _G
The frequency division period (NT _S + Tα) is calculated, and this period and frequency f _L
The difference in frequency is detected by comparing with the period T _{L of} .

[Problems to be solved by the invention]

Usually, since the signals of the frequencies f _G and f _L do not have a synchronous relationship with respect to the phase, the conventional frequency comparison circuit has a drawback that the period comparison becomes indeterminate by T _S of one period of the frequency f _G. .

Meanwhile, a method of relatively small one cycle of the divider units signal of the frequency f _G to the period of the overall increase is taken, also in this way, for one cycle of frequency f _G The output (H, L) becomes indefinite, and it cannot be completely eliminated.

Therefore, an object of the present invention is to provide a frequency comparison circuit in which the accuracy of frequency comparison is improved by eliminating such indeterminacy generated in the comparison output.

[Means for solving problems]

In the frequency comparison circuit of the present invention, as illustrated in FIGS. 1 to 4, the first frequency input is the clock input, and the second frequency input is the second input.
(16) that divides the first frequency input with an arbitrary frequency division ratio using the frequency input of (1) as a reset input, and a first frequency division circuit having a plurality of stages corresponding to the frequency division ratio of the frequency division circuit. Flip-flop circuits (20 _{1 to} 20 ₄ ) are provided, and each first flip-flop circuit is cascaded so that its non-inverted output becomes the data input of the next-stage flip-flop circuit, and the first-stage flip-flop circuit is connected. To the data input of the frequency dividing circuit and to the clock input thereof to the second frequency input, and the frequency hysteresis characteristic is set by the number of stages of the first flip-flop circuit. Frequency comparing means for comparing the frequency between the frequency-divided output of the first frequency input and the second frequency input by each of the flip-flop circuits of 8), a first AND circuit (22) for ANDing each non-inverted output of the first flip-flop circuit of the frequency comparison means, and an inversion of the first flip-flop circuit of the frequency comparison means. A second AND circuit (24) that takes the logical product of the outputs and the output of the first AND circuit are added to the set input, and the output of the second AND circuit is added to the reset input, and the first and second A second flip-flop circuit (26) for generating a comparison output of a frequency input is provided.

[Action]

A first frequency input is added to a clock input of the frequency dividing circuit, and a second frequency input is added to its reset input, and the first frequency input is frequency-divided by the frequency dividing circuit at an arbitrary frequency division ratio. .

Further, the frequency comparison means is configured by the first flip-flop circuit having the number of stages corresponding to the frequency division ratio of the frequency division circuit,
In this frequency comparison means, the frequency-divided output of the frequency-dividing circuit is added to the data input of the first-stage flip-flop circuit, and the second frequency input is added to the clock input of each first flip-flop circuit. , The output is transferred from the flip-flop circuit of the previous stage to the flip-flop circuit of the next stage according to the second frequency input, and the frequency systemissis characteristic based on the frequency dividing operation according to the number of stages of the flip-flop circuit is obtained.

Then, in the first AND circuit, the logical product of the non-inverted outputs obtained in the first flip-flop circuit is obtained, and in the second AND circuit, the inverted output obtained in the first flip-flop circuit is obtained. And the output of the first AND circuit is the set input of the second flip-flop circuit, the second AN
The output of the D circuit is applied to its reset input.

Therefore, the AND output of the first and second AND circuits provides an output from the second flip-flop circuit, which indicates whether the frequencies of the first frequency input and the second frequency input match or do not match.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the drawings.

FIG. 1 shows an embodiment of the frequency comparison circuit of the present invention.

The input signal of the frequency f _G is applied to the input terminal 12 as the first frequency input, and the input signal of the frequency f _L is applied to the input terminal 14 as the second frequency input.

The frequency dividing circuit 16 is configured to _divide the input signal of the frequency f _G , which is the first frequency input, by N, and is reset by the input signal of the frequency f _L , which is the second frequency input. There is.

Further, the frequency hysteresis circuit 18 provided as the frequency comparison means is composed of a first flip-flop circuit having a plurality of (M) stages, and in this embodiment, it is continuously connected as the first flip-flop circuit. It is composed of flip-flop circuits 20 ₁ , 20 ₂ , 20 ₃ , 20 ₄ . That is, the flip-flop circuits 20 ₁ , 20 ₂ , 20 ₃ , 20 ₄ are cascaded so that the non-inverted output Q of the previous stage becomes the data input D of the next stage, and are the divided outputs of the divider circuit 16. The first frequency input signal is applied to the frontmost flip-flop circuit 20 ₁ as the data input D, and the input signal having the frequency f _L is used as the second frequency signal in each flip-flop circuit 20 ₁ , 20 ₂ ,
20 ₃ and 20 ₄ clock input CK.

Flip-flop circuit 20 _1, 20 _2, 20 _3, 20 each non-inverted output Q of ₄ is applied to the first AND circuit 22, flip-flop circuits 20 _1, 20 _2, 20 _3, 20 each inverted output of ₄ It is added to the second AND circuit 24. That is, the first AND circuit 22 obtains the logical product output of the non-inverted outputs Q of the flip-flop circuits 20 ₁ , 20 ₂ , 20 ₃ , 20 ₄ , and the second AND circuit 24 outputs the flip-flop circuit 2
The logical product of the inverted outputs of 0 ₁ , 20 ₂ , 20 ₃ , and 20 ₄ is obtained, and a matched or unmatched output of each output is generated.

The logical product output generated by the first AND circuit 22 is the set input S of the SR flip-flop circuit 26 installed as the second flip-flop circuit, and the logical product output generated by the second AND circuit 24 is It becomes the reset input R, and the SR flip-flop circuit 26 generates a comparison output from the output terminal 28.

According to such a configuration, the data input D of the flip-flop circuit 20 _1, a frequency of the frequency f _G from the frequency divider 16 obtained by N-dividing (period) input is applied, also its clock input A frequency input of frequency f _L is applied to CK. Here, the period T _S of the frequency f _G is given by T _S = 1 / f _G , and the period of the divided frequency appearing in the output of the frequency dividing circuit 16 is 4
T _S = 4 / f _G. On the other hand, the period T _L of the frequency f _L is T _L = 1 / f
Given by _L. That is, the flip-flop circuit 20
₁ indicates that when the data input D = 1 is applied, the data input D = 1 is held at the arrival of the clock input CK = 1, and this D = 1 is held and output until the arrival of the next clock input. It appears at Q and this output Q becomes the data input D of the flip-flop circuit 20 _{2 at} the next stage. The same operation is repeated by the flip-flop circuits 20 ₂ to 20 ₄ .

When the non-inverted output Q of each flip-flop circuit 20 ₁ , 20 ₂ , 20 ₃ , 20 ₄ becomes Q = 1, the AND circuit 22 generates the logical product output, and the SR flip-flop circuit 26 outputs the set output. Is generated, and this becomes the coincident output of the comparison frequency.

Now, the frequency dividing circuit 16 is divided by N, and the frequencies f _G and f _L of the first and second frequency inputs are compared in the relationship of T _L = NT _S , and the flip-flop circuit of the frequency hysteresis circuit 18 is provided. Is an M-stage configuration, Is established. However, in the equations (1) and (2), N is the division ratio when the frequencies are in phase synchronization, N _H is the division ratio at the high threshold, and N _L is the division ratio at the low threshold. is there.

Therefore, the period N _L T _S at the low threshold and the period N _H T _S at the high threshold are given by the following equations (1) and (2): Therefore, as shown in FIG. 2, frequency hysteresis characteristics are obtained.

Here, if the period obtained by dividing the frequency f _G by the division ratio N _G is N _G T _S , when NT _S <N _G T _S <(N + 1) T _S , the indefiniteness of the comparison output disappears. When the comparison output shifts from the high level (H) to the low level (L), or when the comparison output shifts from the L level to the H level, it is possible to prevent the occurrence of vibration such that the outputs H and L are repeated.

Further, since the frequency hysteresis circuit 18 generates frequency hysteresis when M> 2, it is not necessary to increase the frequency dividing stage as in the conventional case, and stable frequency comparison can be realized.

Next, FIG. 3 shows a concrete configuration example of the frequency comparison circuit of the present invention, and the same parts as those of the embodiment shown in FIG. 1 are designated by the same reference numerals.

In this embodiment, the frequency dividing circuit 16 includes the NAND circuits 30, 32 and T.
It is composed of flip-flop circuits 34, 36, 38, 40. That is, the NAND circuit 30 receives the input signal of the frequency f _G and the output of the NAND circuit 32, and when the outputs of both do not match, the NAND circuit 30 generates the output H, and this output H is the T flip-flop. It becomes the trigger input T of the circuit 34. When both the non-inverted output Q of the T flip-flop circuit 34 and the non-inverted output Q of the T flip-flop circuit 40 due to the trigger input T are added to the NAND circuit 32 and the respective output Q do not match, the NAND circuit 32 is Output H is generated. Then, the T flip-flop circuits 34, 36, 38, 40 are connected in the same manner as in the previous embodiment, and in this embodiment, the T flip-flop circuit 40 is connected.
From which a frequency-divided output is obtained, and this frequency-divided output is added to the NAND circuit 32.

The output of the NAND circuit 32 is applied to the data input D of the D flip-flop circuit 42, and the D flip-flop circuit 42 receives the data input D.
An input signal of frequency f _G is inverted by an inverter 44 and applied to a clock input CK of 42. That is, the data input D is held in response to the clock input CK, and its output Q is added to the D flip-flop circuit 46 as the data input D.

In addition, the clock input CK of this D flip-flop circuit 46
A frequency input is applied to the input terminal 14 side.
That is, the input signal of frequency f _L applied to the input terminal 14 is applied to the flip-flop circuit 48 as the trigger input T, its output Q is applied to the D flip-flop circuit 50 as the data input D, and its inverted output is applied to the inverter. 52
Is applied as a clock input CK to the D flip-flop circuit 46 via the
As a reset input R. A frequency input is applied to the D flip-flop circuit 50 from the input terminal 12 as a clock input CK, and its inverted output is passed through the inverter 52 to the T flip-flop circuits 34, 36, 38 ,.
It is added to 40 as a reset input R.

In this embodiment, the frequency hysteresis circuit 18 is composed of five stages of flip-flop circuits 20 ₁ , 20 ₂ , 20 ₃ , 20 ₄ , 20 ₅ , and the frontmost flip-flop circuit 20 ₁ has a D flip-flop circuit. A non-inverted output Q of 46 is added as a data input D, and each flip-flop circuit 20
The inverted output Q of the D flip-flop circuit 50 is inverted and added by the inverter 52 in common to the clock inputs CK of ₁ , 20 ₂ , 20 ₃ , 20 ₄ , 20 ₅ .

The operation of the above configuration will be described with reference to FIG. 4. A in FIG. 4 is an AC signal generated by a frequency generator (not shown), and FIG. 4B is obtained from this AC signal. Of the frequency f _G , which is applied to the input terminal 12.

This input signal is divided by 5 by the frequency dividing circuit 16, and the divided output becomes a pulse as shown in FIG. 4C.

And, D to O of FIG. 4 represent input signals applied to the input terminal 14, and C of FIG.
The timing of the pulse applied to the input terminal 14 is shifted with respect to the repetition of the pulse shown in Fig. 4 to clarify the relationship between the periodic arrival timing of the pulse of frequency f _L with respect to the pulse shown in Fig. 4C. is there.

That is, in this embodiment, the equations (1) and (2) are used.
In, M = 5, N = 5, and NT _S = 10,
From Equation (1), N _L T _S = 10.2 and N _H T _S = 10.8.

When such a relationship is displayed, the pulse period arrives at the timings D to O in FIG. 4, and N _L T _S 10.2
In the relationship of, the five cycles from the arrival of the pulse shown in D of FIG. 4 to the arrival of the pulse shown in I of FIG. 4 (the same as D in FIG. 4) with respect to the pulse of FIG. I need it.

Further, the relationship between N _H T _S = 10.8, take five laps period from the arrival of the pulse of FIG. 4 J to Figure 4 O pulses (the same as FIG. 4 J) arrives.

As a result, frequency hysteresis is obtained, and stable frequency comparison can be realized. For example, it can be used for frequency comparison in mode switching of a video tape recorder.

In the embodiment shown in FIG. 3, the output of the flip-flop circuit 50 can be reset by applying a signal to the reset input R of the D flip-flop circuit 50.
The frequency comparison output can be held. By doing so, there is an advantage that the judgment output of the reproduction mode can be held even during the pause operation in the video tape recorder.

Although the number of flip-flop circuits forming the frequency hysteresis is set to 4 or 5, it may be set to 2, 3 or 6 or more depending on the required frequency hysteresis to obtain a desired frequency hysteresis characteristic. It goes without saying that it will be done.

〔The invention's effect〕

As described above, according to the present invention, a desired frequency hysteresis characteristic can be realized according to the number of stages of the flip-flop circuit, and frequency comparison is performed using this frequency hysteresis characteristic. Can be prevented, and highly reliable and highly accurate frequency comparison can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a frequency comparison circuit of the present invention, FIG. 2 is a diagram showing frequency hysteresis characteristics in the frequency comparison circuit shown in FIG. 1, and FIG. 3 is a frequency comparison circuit of the present invention. FIG. 4 is a block diagram showing a specific embodiment, FIG. 4 is a timing chart showing operation timing of the frequency comparison circuit shown in FIG. 3, and FIG. 5 is a block diagram showing a conventional frequency comparison circuit. 18 ... Frequency hysteresis circuit (frequency comparison means) 20 ₁ , 20 ₂ , 20 ₃ , 20 ₄ , 20 ₅ ...... First flip-flop circuit, 22 ...... First AND circuit, 24 ...... Second AND circuit circuit. 26 ... second flip-flop circuit

Claims (1)

[Claims] 1. A frequency dividing circuit for dividing a frequency of the first frequency input with an arbitrary frequency division ratio, using a first frequency input as a clock input and a second frequency input as a reset input, and a frequency dividing circuit for dividing the frequency. A first flip-flop circuit having a plurality of stages corresponding to the frequency ratio is provided, and each first flip-flop circuit is cascaded so that its non-inverted output becomes the data input of the next-stage flip-flop circuit, The frequency output is applied to the data input of the flip-flop circuit on the first stage side and the second frequency input is applied to the clock input thereof, and the frequency hysteresis characteristic depends on the number of stages of the first flip-flop circuit. A frequency ratio that is set and compares the frequency between the divided output of the first frequency input and the second frequency input by each of the first flip-flop circuits. Comparing means, a first AND circuit that obtains a logical product of the non-inverted outputs of the first flip-flop circuit of the frequency comparing means, and a logic of the inverted output of the first flip-flop circuit of the frequency comparing means. A second AND circuit that takes a product, a set input that is the output of the first AND circuit, and a second AND circuit
And a second flip-flop circuit for generating a comparison output of the first and second frequency inputs, the output of the circuit being applied to a reset input, and a frequency comparison circuit.