JP2901829B2 - Pulse generator for CCD solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator for a CCD (charge coupled device) solid-state imaging device used in a video camera or the like.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 4, a pulse generator of a CCD solid-state imaging device receives a clock, divides this clock by １ ／, and outputs a subclock C1. Frequency dividing circuit 101 and the above-mentioned 1/2 frequency dividing circuit 101
A counter operation pulse forming circuit 102 which receives the sub-clock C1 from the controller and the horizontal scanning reference pulse to form a counter operation pulse, and the counter operation pulse forming circuit 1
02 and the 1/2 frequency dividing circuit 1
The counter circuit 103 counts the subclock C1 from the counter circuit 103 and outputs a count data signal. The counter circuit 103 receives the count data signal from the counter circuit 103 and decodes the count data signal. And a decoder circuit 104 for outputting a decoded data signal. The decoder circuit 104 receives the decoded data signal from the decoder circuit 104 and latches the decoded data.
Some include a latch circuit 105 that outputs a D drive pulse, a pause pulse, and a final pulse. Further, in response to the pause pulse and the clock from the latch circuit 105, a horizontal CCD drive pulse formed by dividing the clock by 出力 is output outside the period in which the stop pulse is output. / 2 frequency dividing circuit 106 and the latch circuit 1
Receiving a rest pulse from the reset circuit 105 and outputting a reset pulse; receiving a reset pulse from the reset circuit 107 and the clock; 1/2 frequency divider 108 that outputs a sub clock C2 synchronized with
And the sub clock C2 from the 分 frequency dividing circuit 108
And a gate circuit 109 that outputs a CDS (correlated double sampling) pulse and a charge reset pulse in synchronization with the horizontal CCD drive pulse. The final pulse from the latch circuit 105 is input to the counter operation pulse forming circuit 102.

The pulse generator of the CCD solid-state imaging device operates as shown in a timing chart of FIG. 5 in synchronization with a horizontal scanning reference pulse and a horizontal blanking pulse from a synchronization signal generator (not shown). As shown on an enlarged time axis in the lower part of FIG. 5, the charge reset pulse and the CDS pulse are continuous pulses whose phases are shifted from each other, and the horizontal CCD drive pulse also has an effective pixel signal period and an optical black signal. In the period of the shaded portion Y including the period,
It is a continuous signal that does not switch. Then, when the horizontal scanning reference pulse goes to H level, the counter operation pulse forming circuit 102 sets the counter operation pulse to H level in synchronization with the sub-clock C1. The counter circuit 103 starts counting the sub-clock C1 in response to the H-level counter operation pulse. Then, based on the decoded data signal generated by decoding the count data signal of the counter circuit 103 by the decoder circuit 104, the latch circuit 105 outputs the optical black signal for a predetermined period after the counter operation pulse becomes H level. The clamp pulse is set to the H level for a predetermined period (a part of the optical black signal period shown in FIG. 5). When the optical black clamp pulse goes low after the predetermined period, the latch circuit 105 outputs vertical CCD drive pulses (A, B, C, and D shown in FIG. 5) out of phase with each other.
The pause pulse is set to the H level for a predetermined period. While the pause pulse is at the H level, the 1/2 frequency dividing circuit 106 stops operating and the output of the horizontal CCD drive pulse stops. Then, the latch circuit 105 outputs the final pulse at the same time as setting the pause pulse to L level after a predetermined period, and the counter operation pulse forming circuit 102 sets the counter operation pulse to L level by this final pulse, The circuit 103 stops counting. Also,
Since the pause pulse goes to the L level, the 1/2 frequency dividing circuit 106 outputs a horizontal CCD drive pulse. Thus, the pulse generator performs the above-described series of operations, and one horizontal blanking period ends.

[0004]

In the conventional CCD solid-state imaging device, when the optical black clamp pulse is at the H level, the black level is determined based on the horizontal CCD drive pulse, the charge reset pulse, and the CDS pulse. Clamp the reference level of optical black, which is the reference for. Then, using this reference level, an output detection circuit (not shown) detects the transferred signal charge.

On the other hand, the counter circuit 103 is usually a binary counter, and outputs Q1, Q2, Q3, Q4 to Q4 of the counter circuit 103 as shown in FIG.
The respective changes of n (only Q1 to Q4 are shown in the figure) are not uniformly performed at each change time point of the subclock C1. That is, the counter circuit 103 starts counting the sub-clock C1 from the reset state (outputs Q1 to Q4 are all 0), and at the rising edge of the first sub-clock C1, only Q1 changes from 0 to 1. Become. Then, at the next rising of the sub clock C1, Q1 becomes 1 →
0 and Q2 change from 0 to 1. As described above, the count advances sequentially, and the change state of each output Q1 to Qn becomes different at each edge of the subclock C1, and the number of outputs that change simultaneously increases or decreases. The change in the operation state of the counter circuit 103 generates count noise.

Therefore, as shown in FIG. 7, count noise from the operating counter circuit 103 is output from the 1/2 frequency dividing circuit 106 including the period when the optical black clamp pulse is at the H level. The gate circuit 10 shown in FIG.
9 and also superimposed on the charge reset pulse and the CDS pulse. Therefore, an optical black clamp unit (not shown) that operates when the optical black clamp pulse is at the H level sets the optical black reference level due to count noise superimposed on the horizontal CCD drive pulse, the reset pulse, and the CDS pulse. There is a problem that the clamp cannot be performed correctly, which adversely affects the detection of the signal charge and deteriorates the image quality.

An object of the present invention is to prevent a counter circuit for generating a vertical drive pulse from operating while an optical black clamp pulse is being output, that is, only during a period during which a CCD solid-state imaging device has no pixel signal. Accordingly, it is an object of the present invention to provide a pulse generator of a CCD solid-state imaging device in which the count noise does not affect the optical black clamp section by operating the optical pickup.

[0008]

In order to achieve the above object, a pulse generator of a CCD solid-state imaging device according to the present invention comprises:
An optical black clamp pulse output circuit that forms and outputs an optical black clamp pulse based on the horizontal scanning reference pulse, a counter circuit that counts clocks to form a vertical drive pulse, and the optical black clamp pulse are output And a horizontal drive pulse output circuit for forming and outputting a horizontal drive pulse based on the clock during a predetermined period including the above period, wherein the optical black clamp pulse output circuit A delay circuit that outputs a delay signal created by delaying the horizontal scanning reference pulse, and a logic circuit that receives the delay signal output from the delay circuit and forms the optical black clamp pulse. , From the delay circuit A counter operation pulse forming circuit for forming a counter operation pulse for operating the counter circuit after the output of the optical black clamp pulse is stopped based on the extension signal, and outputting the counter operation pulse to the counter circuit. Pulse generator for CCD solid-state imaging device.

[0009]

When the horizontal scanning reference pulse is input to the pulse generator of the CCD solid-state imaging device having the above configuration, the delay circuit outputs a delay signal created by delaying the horizontal scanning reference pulse. The logic circuit receives the delay signal output from the delay circuit and forms an optical black clamp pulse. On the other hand, after the output of the optical black clamp pulse is stopped based on the delay signal from the delay circuit, the counter operation pulse forming circuit outputs a counter operation pulse for operating the counter circuit. Upon receiving the counter operation pulse, the counter circuit counts a clock to form a vertical drive pulse. The horizontal drive pulse output circuit forms and outputs a horizontal drive pulse based on the clock, including the period during which the optical black clamp pulse is output.

As described above, the counter circuit does not count during the period in which the optical black clamp pulse is output. Therefore, the horizontal CCDs simultaneously output during the output period of the optical black clamp pulse.
The drive pulse is not affected by the count noise from the count circuit. Therefore, the reference level of the optical black can be correctly clamped, and the deterioration of the image quality can be prevented.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A pulse generator of a CCD solid-state imaging device according to the present invention will be described below in detail with reference to an embodiment.

FIG. 1 is a block diagram of a pulse generator of a CCD solid-state image pickup device according to an embodiment of the present invention. Reference numeral 1 denotes a 1/2 which divides a clock by 1/2 and outputs a subclock C1. The frequency dividing circuit 2 receives the sub clock C1 from the 1/2 frequency dividing circuit 1 and a horizontal scanning reference pulse from a synchronization signal generator (not shown), delays the horizontal scanning reference pulse, and reduces the delay amount. The delay circuit 3 is composed of a shift register that outputs two different delayed horizontal scanning reference pulses H1 and H2. A gate circuit 4 as an example of a logic circuit that outputs the sub clock C1 from the 分 frequency divider 1 and the delayed horizontal scanning reference pulse H2 from the delay circuit 2 The counter operation pulse forming circuit 5 that outputs the counter operation pulse receives the counter operation pulse from the counter operation pulse forming circuit 4 and the subclock C1 from the 分 frequency dividing circuit 1, and generates the subclock C1. A counter circuit 6 for counting receives a count data signal from the counter circuit 5 and a decoder circuit for decoding the count data signal. A 7 receives a decode data signal from the decoder circuit 6 and
A latch circuit that latches the decoded data and outputs a vertical CCD drive pulse, a pause pulse, and a final pulse. 8 is a 1/2 frequency dividing circuit which receives the pause pulse from the latch circuit 7 and the clock, divides this clock by 1/2, and outputs a horizontal CCD drive pulse;
A reset circuit 9 receives a pause pulse from the latch circuit 7 and outputs a reset pulse, and a reset circuit 10 receives a reset pulse from the reset circuit 9 and the clock and divides the clock by １ ／. , Which outputs a sub clock C2 synchronized with the horizontal CCD drive pulse.
The frequency dividing circuit 11 is provided with a horizontal C from the 1/2 frequency dividing circuit 10.
Upon receiving the sub clock C2 synchronized with the CD drive pulse,
The gate circuit 11 outputs a charge reset pulse for resetting signal charges and a CDS (correlated double sampling) pulse for reducing low-frequency noise of a detection signal. The last pulse from the latch circuit 7 is input to the counter operation pulse forming circuit 4.

The pulse generator of the CCD solid-state image pickup device having the above-described configuration synchronizes with a horizontal scanning reference pulse and a horizontal blanking pulse periodically output from a synchronization signal generator (not shown) for each horizontal scanning. The operation is performed as shown in the timing chart of FIG.

That is, the horizontal C of the 1/2 frequency dividing circuit 8
The CD drive pulse is a continuous signal that does not switch during the period of the hatched portion X shown in FIG. 2, and the charge reset pulse and the CDS pulse output from the gate circuit 11 are also continuous signals. The horizontal scanning reference pulse is for a predetermined period H
At the same time, the horizontal blanking pulse goes high during the horizontal blanking period. When the horizontal scanning reference pulse goes to the H level, the delay circuit 2 composed of a shift register delays the horizontal scanning reference pulse in synchronization with the sub-clock C1 from the 1/2 frequency dividing circuit 1, and delays the horizontal scanning reference pulse H1. And the delayed horizontal reference pulse H having a longer delay time than the delayed horizontal reference pulse H1 and having its logic inverted.
2 is output. Upon receiving the delayed horizontal reference pulses H1 and H2 from the delay circuit 2, the gate circuit 3 takes the logical product of the delayed horizontal reference pulses H1 and H2. The black clamp pulse is set to the H level. That is, the leading edge of the optical black clamp pulse is defined by the leading edge of the delayed horizontal reference pulse H1, and the trailing edge of the optical black clamp pulse is defined by the trailing edge of the delayed horizontal reference pulse H2. The optical black clamp pulse is input to an optical black clamp unit (not shown) and clamps an optical black reference level serving as a black level reference. Further, when the delayed horizontal reference pulse H2 changes from the H level to the L level, the counter operation pulse of the counter operation pulse forming circuit 4 changes to the H level, and the counter circuit 5 outputs the sub-signal from the 1/2 frequency dividing circuit 1. The clock C1 starts counting. The leading edge of the counter operation pulse is defined by the leading edge of the delayed horizontal reference pulse H2. Then, the count data signal of the counter circuit 5 is decoded by a decoder circuit 6, and the decoded data is latched by a latch circuit 7 so that the vertical CCD drive pulses (A, B, C,
D) is output. When a predetermined time elapses after the delayed horizontal reference pulse H2 changes from the H level to the L level, the latch circuit 7 outputs a pause pulse for a predetermined period (a part of the output period of the horizontal blanking pulse). Period) H
To level. When the pause pulse goes to H level, the frequency dividing circuit 8 stops the frequency division and sets the horizontal CCD drive pulse to H level. When the pause pulse of the latch circuit 7 changes from L level to H level, the reset circuit 9 outputs a reset pulse. Note that the reset circuit 9 changes the pause pulse of the latch circuit 7 from H level to L level.
A reset pulse may be output when the level becomes the level. By the reset pulse, the 1/2 frequency dividing circuit 1
0 is reset, and the charge reset pulse and the CDS pulse output from the 1/2 frequency dividing circuit 10 are transferred to the horizontal CCD.
Synchronize with drive pulse. Then, the latch circuit 7 stops outputting the vertical CCD drive pulse, sets the pause pulse to the L level after a predetermined period, and then outputs the final pulse. With the final pulse, the counter operation pulse forming circuit 4 sets the counter operation pulse to the L level. When the counter operation pulse goes low, the counter circuit 5 stops counting. Further, the 1/2 frequency dividing circuit 8 starts frequency division of the clock in response to the L level of the pause pulse, and outputs the horizontal CCD driving pulse.
Then, when the horizontal blanking period ends, the horizontal blanking pulse goes to L level. Thereafter, when one horizontal scan is completed, the horizontal blanking period starts again, and the above-described series of operations is repeated.

As described above, the conventional method of forming the optical black clamp pulse by using the counter circuit is replaced by the delay circuit 2 comprising the shift register, as shown in FIG. The delay pulses D1 to Dn whose phases are sequentially shifted by one clock of the clock C1 are formed. For example, an optical black clamp pulse is formed by the gate circuit using the delay pulse D1 and the delay pulse D2. I have. In this case, since only one of the delay pulses D1 to Dn changes uniformly for each leading edge of the subclock C1, no count noise is generated unlike the counter circuit. Therefore, the counter circuit 5 does not count the sub clock C1 during the period in which the optical black clamp pulse is output. The pulse is not affected by the count noise from the counter circuit 5 and is not affected by the noise from the delay circuit 2. Therefore, the optical black clamp unit (not shown) of the CCD solid-state imaging device can correctly clamp the optical black reference level without being affected by noise, and can prevent deterioration in image quality.

In the above embodiment, the delay circuit 2 is １ ／
Although the horizontal scanning reference pulse is delayed by the shift register using the subclock C1 from the frequency dividing circuit 1, the method of delaying the horizontal scanning reference pulse is not limited thereto, and a clock, a timer, or the like built in the delay circuit may be used.

Further, in the above embodiment, upon receiving the delayed horizontal reference pulses H1 and H2 from the delay circuit 2, the gate circuit 3 takes the logical product of the delayed horizontal reference pulses H1 and H2 to generate the optical black clamp pulse. However, the combination and the logic condition of the delayed horizontal reference pulse are not limited to this.

In the above embodiment, the clock is set to 1
Although the sub-clocks C1 and C2 divided by two were used,
An appropriate frequency division ratio such as frequency division by 3, frequency division by 1/4, frequency division by 1/5, etc. may be used.

[0019]

As is clear from the above, the C of the present invention
When the horizontal scanning reference pulse is input to the pulse generator of the CD solid-state imaging device, the delay circuit outputs a delay signal created by delaying the horizontal scanning reference pulse, and receives the delay signal from the delay circuit. The logic circuit forms an optical black clamp pulse, and based on the delay signal from the delay circuit, the counter operation pulse forming circuit operates the counter circuit to operate the counter circuit after the output of the optical black clamp pulse is stopped. The counter circuit receives the counter operation pulse, counts a clock to form a vertical drive pulse, and the horizontal drive pulse output circuit outputs a pulse during which the optical black clamp pulse is output. Generates horizontal drive pulse based on clock during specified period And outputs Te.

Therefore, according to the pulse generator of the CCD solid-state imaging device of the present invention, the counter circuit does not count the clock during the period in which the optical black clamp pulse is output. The output horizontal drive pulse or other signal is not affected by the count noise from the count circuit. Therefore,
The reference level of the optical black can be correctly clamped, and a CCD solid-state imaging device with stable image quality as compared with the related art can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a pulse generator of a CCD solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a timing chart of a pulse generator of the CCD solid-state imaging device.

FIG. 3 is a timing chart of a delay circuit of a pulse generator of the CCD solid-state imaging device.

FIG. 4 is a block diagram of a pulse generator of a conventional CCD solid-state imaging device.

FIG. 5 is a timing chart of a pulse generator of the conventional CCD solid-state imaging device.

FIG. 6 is a timing chart of a counter of a pulse generator of the conventional CCD solid-state imaging device.

FIG. 7 is a timing chart including the timing of a counter of a pulse generator of the conventional CCD solid-state imaging device.

[Explanation of symbols]

1, 8, 10 ... 1/2 frequency dividing circuit, 2 ... delay circuit, 3, 1
1 gate circuit, 4 counter operation pulse forming circuit, 5
... Counter circuit 6 ... Decoder circuit, 7 ... Latch circuit, 9 ... Reset circuit.

Claims (1)

(57) [Claims] An optical black clamp pulse output circuit that forms and outputs an optical black clamp pulse based on a horizontal scanning reference pulse; a counter circuit that counts clocks to form a vertical drive pulse; A pulse generator for a CCD solid-state imaging device having a horizontal drive pulse output circuit that forms and outputs a horizontal drive pulse based on the clock during a predetermined period including a period during which a clamp pulse is output; The black clamp pulse output circuit is
A delay circuit that outputs a delay signal created by delaying the horizontal scanning reference pulse; and a logic circuit that receives the delay signal output from the delay circuit and forms the optical black clamp pulse. A counter operation pulse forming circuit that forms a counter operation pulse for operating the counter circuit after the output of the optical black clamp pulse is stopped based on the delay signal from the delay circuit and outputs the counter operation pulse to the counter circuit. A pulse generator for a CCD solid-state imaging device.