JPS6018065A - Drive circuit of solid state image pickup element - Google Patents

Abstract

PURPOSE:To increase the phase margin by selecting the polarity of division output in accordance with the result of phase comparison between a synchronizing signal and the division output of the output of an oscillator, and obtaining various types of driving pulses from a shift register which is driven by the division signal. CONSTITUTION:The output of a crystal oscillator 16 is sent to a frequency divider 18 and to a synchronizing signal generator 17. A phase detecting circuit 19 performs the phase comparison between the output of the divider 18 and the pulse signal of horizontal scanning period of the generator 17. The polarity of the divider 18 is selected in accordance with the result of said phase comparison. The selected signal is sent to a shift register 21 via a dividing circuit 27, and the output of the register 21 is converted into various types of driving pulses by decoders 23 and 24. Thus the phase margin is increased even though a phase difference produced between a pulse of horizontal scan period and an oscillation output signal. In such a way, the generation of the horizontal reading jitter is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a driving circuit for a solid-state image sensor.

Conventional Structure and Problems First, a general outline of a solid-state image sensor will be explained using FIG. 1. However, FIG. 1 shows a configuration for deepening understanding of a solid-state image sensor, and the present invention can be applied to a drive circuit for a solid-state image sensor of any configuration.

In FIG. 1, 1 is a solid-state image sensor, 2 (2a).

2b...) is a 7A todai auto which is a light receiving section.

3 (3a, 3b...) are vertical signal lines, each connected to a photodiode. In other words, the photoguiot 2a of the first horizontal line in FIG. 1 has a vertical switching MOS-FET 4 (4a
, 4b--=). Reference numeral 5 designates a vertical shift register, and this vertical scintill register 5 has input terminals for vertical scanning pulse φsP and clock pulse φV, and the output terminal of each stage of vertical shift register 5 is connected to vertical address line 6 (6a, e+b , -) through the MO8
- Commonly connected to the gates of one horizontal line of FET4. Also, one end of the vertical signal line 3 is connected to the transfer 1tvjO3.
-FET7 (7a, '7b'''-).The gates of these MOS-FET7 are connected in common and connected to the transfer gate input (φTB).This transfer gate 7 A charge-coupled horizontal shift resistor (hereinafter abbreviated as horizontal COD) 8 is arranged adjacent to the , and one end in the horizontal direction is connected to the signal output section 9. The structure of the element is described above, and next, the structure of the element is explained. The operation will be explained. Signal charges are accumulated in the photodiode 2 by the incident light from the object during one vertical period.

Next, a vertical scanning pulse φsP and a vertical clock pulse φV are supplied to the vertical shift register 6 to operate the vertical shift register.

A vertical scanning pulse generated from the vertical shift register 6 is applied to the gate of the vertical switch MO3-FET4, and the signal charge accumulated in the photodiode 2 is transferred onto the vertical signal line 3. Next, by applying a voltage to the transfer gate 7, the data is transferred to the horizontal CCD 5. The signal charge transferred to the horizontal CCD 5 becomes 1 due to the horizontal transfer lock φH described below.
During the horizontal scanning period, the signals are sequentially transferred to the signal output section 9 and read out. The frequency of this horizontal transfer lock is determined by the number of photodiodes arranged in one horizontal line. In the case of 384 photodiodes, the frequency is approximately 7.2 MHz. The solid-state imaging device used in this circuit is based on the operating principle described above.

FIG. 2 shows specific examples of drive pulse waveforms for vertical two-phase drive, horizontal four-phase drive, and horizontal output section reset pulses for the solid-state image sensor.Actual drive pulses are even more complex.

Next, a configuration example and problems of a conventional solid-state image sensor driving circuit will be described with reference to FIGS. 3 and 4.

In FIG. 3, reference numeral 10 denotes a crystal oscillator, whose output signal is divided by an integer (-) by a divider 11 to obtain a horizontal drive pulse φH. Furthermore, the oscillator output signal is divided into a frequency divider 12.
．． The frequency is divided by 13, and the signals at each stage of the divided period are sent to the decoder 1.
4 to obtain each drive pulse. Each drive pulse of the decode output signal is a vertical clock pulse of a vertical shift register, a transfer gate pulse, etc. Here, in order to synchronize each drive pulse with horizontal scanning, the oscillator output signal is supplied to a synchronization signal generator 16 consisting of a 1-chip monolithic IC, and the pulses of the horizontal scanning period (hereinafter abbreviated as HD) and the vertical scanning period are A pulse (hereinafter abbreviated as VD) is obtained, and the pulse (HD) of the horizontal scanning period is divided into periods 12.
13 to reset the dividing periods 12 and 13 and synchronize the output signals of the frequency dividers 12 and 13 with the HD.

Since the horizontal transfer pulse φH must also be synchronized with the HD, the output signal of the decoder 14 is supplied to the frequency divider 11 to reset the frequency divider 11 and synchronize the horizontal transfer pulse φH with the HD. The horizontal transfer pulse and each drive pulse are obtained by the solid-state image sensor drive circuit configured as described above.

However, when a solid-state image sensing device driving circuit having the above-mentioned configuration was actually manufactured and operated, several problems occurred.

The first problem is that the phase of the HD output signal of the synchronization signal generator 15 shown in FIG. 3 is relatively shifted from the phase of the input signal, that is, the oscillator output signal.
Temperature changes, power supply voltage changes, and variations in the elements of the synchronization signal generator themselves are interrelated. Therefore, the phase of the reset signal of the frequency divider 11.12.degree. 13 is shifted relative to the oscillator output signal. To explain the state of
The relationship is 3φH4, but if the HD start-up phase changes to the middle of the time between t2 and t3 due to temperature changes, etc., φφ
The relationship is 1Hs' H4 However, the rising phase of HD and the relative phase of 141ViH2 gradually change due to temperature fluctuations. Therefore, if HD exists near time t2 shown in FIG. 4, φH1
The signal is either φH1 or φH1'. (The instability will continue as described above until the temperature further fluctuates and the rise of HD changes sufficiently from the position of time t2 and stabilizes.) A dark image will be a horizontal shift, for example, if a vertical line is imaged. , the horizontal edges become jagged.

The second problem is that, as shown in FIG. 4, the pulses of φH and φH/ are relatively inverted. This converts the output stage of the horizontal CD into FDA (Frotting Diffusion).
Amplifier) If the floating diffusion is reset, the phase relationship with the φR pulse is reversed between φH and φ) (/, so the FD
A will no longer function properly.

As described above, in the conventional example, the phase fluctuation tolerance of the HD that prevents the phase of the horizontal transfer pulse from shifting is limited to the period from tl to t2-1, that is, Tons (, Tons).

However, FIG. 5 shows the temperature characteristics of the phase relationship between the HD output signal of the synchronizing signal generator configured with the current one-chip monolithic IC and the oscillator output signal, that is, the long signal to the synchronizing signal generator. Unfortunately, the variation in the elements of the synchronization signal generator itself is about 20 ns in absolute value. Therefore, assuming that the temperature fluctuation takes 32 ns and the initial value variation takes 920 ns, the above-mentioned phase fluctuation tolerance is 70 n.
s, it is not possible to completely prevent horizontal transfer jitter.

That is, as shown in FIG. 4, the rise of HD is at time t2.
If it exists in the vicinity of , there will be almost no phase fluctuation tolerance.

Furthermore, if the configuration based on a frequency divider as shown in FIG. 3 is used to obtain various drive pulses, there is a drawback that it is difficult to obtain complicated drive pulse timings for the solid-state image sensor. Furthermore, since the drive pulse is determined by the structure of the solid-state image sensor, it is difficult to use a solid-state image sensor drive circuit that has been once designed as a drive circuit for another solid-state image sensor. Furthermore, when the drive circuit is made into a monolithic IC, it often becomes complicated.

Purpose of the Invention The present invention does not cause horizontal read jitter, and furthermore,
The object of the present invention is to provide a solid-state image sensor driving circuit that can arbitrarily select the driving pulse timing and easily change the driving pulse timing, that is, is suitable for IC implementation.

Structure of the Invention The present invention provides a solid-state imaging system that includes an oscillator, a frequency divider that divides the oscillator output signal →-, and a synchronization signal generator that obtains the timing of a horizontal scanning period and a vertical scanning period from the oscillator output signal. In the element 1 drive circuit, the polarity of the output signal of the frequency divider is selected based on the signal obtained by comparing the phase of the horizontal scanning period pulse (HD) of the synchronizing signal generator and the output signal of the sufficient frequency divider. A shift register is driven by the frequency divider output signal, and a solid-state image sensor driving pulse is obtained by decoding the output signal of each stage of the shift register.

Description of examples Embodiments according to the present invention will be described below with reference to the drawings.

FIG. 6 shows a block diagram of a solid-state image sensor driving circuit in an embodiment of the present invention. In Figure 6, 1
6 is a 14 MHz crystal oscillator that serves as the source oscillation. 1
Reference numeral 7 denotes a synchronization signal generator that generates HD, VD signals, etc. synchronized with horizontal scanning and vertical scanning. The frequency of the output signal of 16 is divided into 1/2 by the frequency divider 18, and the frequency of the output signal of 16 is divided into 1/2 by the frequency divider
Among the output signals of No. 7, the phase of HD (p) is compared with the phase of No. 13 by a phase detection circuit 19, and depending on the output signal, either the output of No. 13 or its inverted signal is selected by a selector 20. The resulting signal is further divided into 1/3 by a frequency divider 27, and the signal is used as a clock, and the HD signal is used as data to operate the 24-stage soft register 21.
A signal delayed by 24 frequency-divided pulses of 1/6 of the original oscillation frequency is output. The output of the final stage is used as a reset signal for each stage. Then, using the output signal of the selector 20 as data, the output signal of the selector 20 is used as a clock, delayed by the shift register 22, and decoded by the decoder 23. Further, depending on the configuration of the solid-state image sensor, if it is not necessary to generate drive pulses with very fine timing, the signals of each stage of the shift register 21 may be decoded by the decoder 24 to obtain each drive pulse.

On the other hand, regarding the horizontal transfer pulse, the gate circuit 25 uses the output signal of the selector 2Q and the output signal of the decoder 23 as data for the latch circuit 26, and latches the signal selected by the selector 20 as a clock. The resulting signal is obtained as a horizontal transfer pulse. As mentioned above, in contrast to the conventional method in which horizontal transfer pulses are generated from 14MHz, in this embodiment horizontal transfer pulses are generated at 7.2MHz.
It will be made from Hz, and the horizontal scanning period pulse and 14M
The Hz phase tolerance is 140 ns, which is double that of the conventional method.

Figure 7 shows the reason why the phase tolerance increases to 140 ns.

This will be explained using FIG.

In FIG. 7, 16 (l-1: original oscillator, 17 is a synchronizing signal generator, 18 is a 1/2 frequency divider consisting of a D flip-flop (hereinafter abbreviated as D-F/F), and 19 is a D-F/F). This is a selector circuit consisting of 20 phase detection circuits consisting of F and AND-○R circuits.

If the output signal t/'i of the original oscillator 16 has the waveform shown as 14 MHz in FIG. 8, the waveform of the output Q1 of the frequency divider 18 will be either S or T in FIG. It is not decided whether the waveform will be S or T.

In order to widen the phase tolerance, if there is a rising edge of WHD near the rising edge of the output signal Q1 of the frequency divider 18,
That is, if there is a phase relationship between 14 MHz and T and U, the output of the selector 20 selects S, and if there is no rising edge of WHD near the rising edge of 01 of the output signal of the frequency divider 18, that is, 14 MHz and T. (7) If there is a phase relationship, the output of the selector 2o is depressed so that T is selected. If the operation of the frequency divider 18 shown in FIG. The logic shown in Figure 7 can be rearranged so that it is outputted.)
The phase variation tolerance between D and 14 MHz is ±70ns, resulting in a phase variation tolerance of 140ns. In Figure 8, S/
, T/ is the output signal of the seventh Kasumi D-F/F21,
This pulse is necessary to detect whether or not the rising edge of HD exists near the rising edge of the output signal of the frequency divider 18.

Furthermore, the RSS flip-flop circuit and DF/F 29 shown in FIG. 7 are for preventing the phase detection circuit 19 from operating all the time. That is, the phase detection circuit according to the present invention may be operated only for a moment when the power to the solid-state image sensor driving circuit is turned on (approximately the time when the first VD is generated after the power is turned on).

As explained above, according to the present invention, regardless of whether the phase relationship between HD and 14MHz is U or U', the phase tolerance is 1.
It satisfies 40ns.

Next, a comparison between the case where the shift register according to the present invention is used and the case where the conventional frequency divider is used will be explained below with reference to FIG. If you want to create the output φTB from the clock signal in Figure 9, the first stage output a of the shift register, the second stage output b
, the third stage output C14th stage output d may be decoded. At this time, each stage of the shift register is reset by the output of the final stage, so by arbitrarily selecting the number of stages of the shift register, the reset timing can be determined, which is even more convenient. By using /stars, a regular and easy circuit configuration can be achieved.

That is, when the timing of the element drive pulse is arbitrarily selected or changed, the configuration is also very advantageous when implementing the drive circuit into an IC.

Although the present invention has been described above with reference to a CCD type solid-state image sensor, it goes without saying that it can also be applied to drive circuits of other systems, such as MOS type solid-state image sensors.

Effects of the Invention As explained above, according to the present invention, even if the phase of the horizontal scanning period pulse and the original oscillation output signal deviate, the phase tolerance is twice that of the conventional example, so it can be sufficiently cleared. , the occurrence of horizontal read jitter can be prevented. Furthermore, since it is composed of shift registers, within a certain horizontal period,
If the drive pulses are arbitrarily selected or changed, a regular and simple circuit configuration that is advantageous for IC implementation can be obtained.

[Brief explanation of drawings]

Figure 1 d: A circuit diagram showing an overview of the solid-state image sensor, Figure 2 is a timing chart showing drive pulses of the solid-state image sensor,
Fig. 3 is a conventional drive circuit block diagram, Fig. 4 is a timing chart of drive pulses obtained in the conventional example, Fig. 5 is a characteristic diagram showing the temperature characteristics of the phase of the horizontal synchronization signal, and Fig. 6 is the invention according to the present invention. 7 is a block diagram showing one embodiment of the drive circuit of the present invention, FIG. 7 is a diagram for explaining the discrimination function of the present invention, FIG. 8 is a timing chart of FIG. 7, and FIG. 9 is a diagram showing the use of a shift register in the present invention. This is a timing chart that explains the benefits of eating on the spot. 1... Original oscillator, 2... Synchronous signal generator, 3
... Frequency divider, 4... Phase detector, 5...
Selector, 7...Shift register, 13...-
・Decoder. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 T + Open Figure 3: 114 Figure 5 Figure 7 Figure 9 C Figure 8 He +4171 "71
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□111.3゜□7゜41n)! ;

Claims (3)

[Claims] (1) It has an oscillator, a frequency divider that divides the frequency of the oscillator output signal into an integer, and a synchronization signal generator that obtains the timing of a horizontal scanning period and a vertical scanning period from the oscillator output signal, and A solid-state image pickup device drive characterized in that the phase of the output signal of the frequency divider is selected based on a signal obtained by comparing the phases of the output signal of the frequency divider and the pulse of the horizontal scanning period of the synchronization signal generator. circuit. (2) A special W characterized in that the frequency division ratio of the frequency divider is 10.
1. A solid-state image sensor driving circuit according to claim 1. (3) The oscillator output signal is frequency-divided, the frequency-divided signal drives a shift register, and the output signal of each stage of the shift register is decoded. solid-state image sensor drive circuit.