JPH0216064B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscillation device used in a synchronization signal oscillation circuit of an imaging device using a solid-state imaging device, and particularly to an oscillation device that stabilizes the oscillation frequency.

Solid-state imaging devices photoelectrically convert light incident on the surface of the device using photoelectric conversion elements such as photodiodes arranged two-dimensionally on the surface of the device, or photoelectric conversion films formed on the surface of the device. This is an element that can read out optical information as an electrical signal by sequentially scanning the signal detection sections in the horizontal and vertical directions. Therefore, in an imaging device using a solid-state image sensor (hereinafter referred to as a solid-state imaging device), the horizontal frequency (hereinafter referred to as a
A clock pulse (hereinafter referred to as a horizontal clock pulse) having a repetition frequency that is an integral multiple of _fH (referred to as fH) is used. The reason for this is explained below.

Since the video signal output from the solid-state image sensor is obtained in synchronization with the horizontal clock pulse, the phase of the horizontal clock pulse with respect to the horizontal period of the television signal determines how the image captured by the imaging device is reproduced on the screen of a monitor TV receiver, etc. Determine the image position on the screen for the case. Therefore, if the phase of the horizontal clock pulse varies with respect to the horizontal period of the television signal, the position of the reproduced image on the screen will vary, resulting in a very unsightly image. Therefore, the horizontal clock pulse is set to a frequency that is an integral multiple of _fH to prevent the above phase shift.

By the way, the horizontal clock pulse frequency is
A periodic signal generating circuit having the configuration shown in Figure 1 has already been proposed as a periodic signal generating circuit that does not cause the above-mentioned phase shift even if a free frequency is set without limiting the frequency to an integer multiple of _fH . No. 56-170017 (Unexamined Japanese Patent Publication No. 1983-
Publication No. 71784)). In Figure 1, f _H
From the output of the oscillator 1 which oscillates at a frequency that is an integer multiple of , a pulse 4 having a repetition frequency f _H as shown in FIG. T _H in FIG. 2 indicates one horizontal scanning period (1/f _H ). This pulse 4 is input to an oscillator 5 for generating horizontal clock pulses. The waveform of the output 6 of the oscillator 5 is shown in FIG. Oscillator 5 oscillates when pulse 4 is at “1” level, and becomes “0”
If the configuration is such that the level oscillation is stopped, the output 6 will have the waveform shown in FIG. 26. If this output 6 is waveform-shaped by an inverter circuit, which is a known digital circuit (not shown), it will be shown in FIG.
The pulse shown is obtained. If this is used as a horizontal clock pulse, the phase is controlled to be constant for each horizontal period, so it can be used not only when the horizontal clock pulse has a repetition frequency that is an integer multiple of _fH , but also when it is not necessarily an integer multiple of _fH . The above-mentioned image position fluctuation does not occur.

As a specific example of the oscillator 5, the configuration shown in FIG. 3 can be considered. In FIG. 3, 8 is a digital circuit called a well-known Schmitt trigger 2-input NAND gate. When a resistor 9 and a capacitor 10 are connected as shown, and a pulse 4 is input to the input terminal 11, the input becomes "1" level. The circuit has the function of oscillating at times and stopping the oscillation operation at the "0" level, and the output 6 is as shown in FIG. 2.

However, the oscillator illustrated in FIG. 3 generally has a characteristic that its oscillation frequency fluctuates significantly as the operating power supply voltage fluctuates or the temperature of the circuit elements fluctuates. When the oscillation frequency of the oscillator 5 changes, the pulse 4 changes from the "0" level to the "1" level in FIG.
Although the phase of the output 6 at the time it changes to level remains constant, the repetition period of the output 6 will expand or contract, and the repetition period of the horizontal clock pulse 7 will similarly vary, which will affect the playback on the monitor television receiver. This results in a change in the horizontal size of the image. That is, in the conventional example, there was a problem in that the horizontal size of the reproduced image expanded or contracted due to fluctuations in the operating power supply voltage or temperature of the circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide an oscillation device that eliminates the above-mentioned disadvantages of the prior art and can maintain a stable oscillation frequency even with fluctuations in operating power supply voltage or temperature fluctuations of circuit elements.

In order to achieve the above object, the features of the present invention are as follows:
The oscillator 5 for generating horizontal clock pulses in the configuration shown in FIG. 1 is constituted by a so-called voltage-controlled oscillator whose oscillation frequency is variable by an external input control voltage, and its oscillation operation is temporarily stopped as described above. , from the time when the oscillation operation starts again, the repetition frequency generated in the same way as pulse 4 from the oscillator with a predetermined pulse phase of the oscillator output 6 or the horizontal clock pulse 7 and an integer multiple of f _H is f _H
The oscillation frequency of the voltage-controlled oscillator 5 is controlled so that the phase of the pulse having a phase different from the stop phase of the oscillator 5 always coincides with the phase of the pulse.

The present invention will be explained below with reference to the drawings.

FIG. 4 is a block diagram of an embodiment of the present invention, and FIG. 5 is a waveform diagram of signals of various parts thereof, and parts having the same functions are denoted by the same reference numerals. In FIG. 4, an oscillator 5 generates a horizontal clock pulse using a pulse 4 with a repetition frequency f _H obtained from an oscillator 1 that oscillates at an integral multiple of f _H via a frequency divider 2 and a decoder 3.
The operation for controlling is the same as the conventional example shown in FIG. In FIG. 4, from the output 6 of the oscillator 5 to the frequency divider 1
2. A pulse 14 having the pulse phase of the n-th oscillation output 6 is obtained via the decoder 13 from the time when the oscillator 5 once stops and then starts oscillating. In this case, the frequency divider 12 is supplied with the oscillator 5 by the pulse 4.
If the configuration is such that the reset is applied at the same timing as the operation stop control, it is easy to obtain the pulse 14 using known digital circuit technology.

On the other hand, in the same way as pulse 4 is obtained from the output of oscillator 1, the operation stop period of oscillator 5 (see FIG.
A pulse 15 is obtained which has a phase different from t _S ) (a in FIG. 5) and whose repetition frequency is f _H . The pulses 14 and 15 are input to the phase detection circuit 16, and the detected output is smoothed through the low-pass filter 17, and the DC voltage is used as the input control voltage of the voltage-controlled oscillator 5.

The fact that the oscillation frequency of the oscillator 5 can be stabilized by the above will be explained below. In FIG. 5, the phase at which the pulse 14 changes from the "1" level to the "0" level depends on the frequency of the oscillator output 6.
5 varies as shown by the broken line. Here, the oscillator 5 is set so that the phase of the pulse 14 changing from the "1" level to the "0" level is always the phase a.
By controlling the frequency of , the following relationship is maintained.

f ₀ = (n-1)/(T ₁ -t) ...(1) However, f ₀ is the oscillation frequency of the oscillator 5, T ₁ and t
are the times shown in FIG. 5, respectively. Here, T ₁
The stability of the value of T1 depends on the frequency stability of the oscillator 1, but by configuring the oscillator 1 with a crystal oscillator or the like, _T1 can be kept at a substantially constant value. Therefore, the factor that causes f ₀ in equation (1) to vary is the variation in t. When the oscillator 5 has the conventional configuration shown in FIG. 3, it is difficult to avoid that the above-mentioned t fluctuates due to fluctuations in the operating power supply voltage or fluctuations in the temperature of the circuit elements. However, in equation (1), if T ₁ is made sufficiently large with respect to t, the fluctuation of f ₀ due to the fluctuation of t can be made low. For example, if T ₁ is set to 50 times t, even if t fluctuates between t±t/2 (fluctuation range of 50%), the fluctuation range of f ₀ can be suppressed to approximately ±1%. When the conventional configuration shown in Fig. 3 is used for the oscillator 5 shown in Fig.
10%), ambient temperature +25℃±35℃)
Frequency fluctuations of ~20% are difficult to avoid. On the other hand, the fourth
According to the embodiment of the present invention shown in the figure, frequency fluctuations can be reduced by setting the ratio between t and _T1 according to the desired frequency stability.

FIG. 6 shows an embodiment of the phase detection circuit 16 shown in FIG. 4, and FIG. 7 shows signal waveforms of various parts thereof. An OR circuit 19, an AND circuit 20, a p-channel MOS transistor 21, and an n-channel MOS transistor 22 are connected as shown. S, D, and G of the MOS transistors indicate the source, drain, and gate, respectively, and the p-channel MOS transistor 2
The source of MOS transistor 22 is connected to a power source having a positive polarity with respect to ground, and the source of n-channel MOS transistor 22 is connected to ground. Pulses 14 and 15 in FIG. 5 are input to input terminals 23 and 24, respectively. When the phase of the pulse 14 deviates from the phase a of the pulse 15 as indicated by a broken line b, a "0" level is output to the OR circuit output 25. At this time p channel
The MOS transistor 21 becomes conductive, and the output 26 becomes a positive voltage with respect to the ground only while the OR circuit output 25 is at the "0" level. Moreover, when the phase of the pulse 14 becomes as shown by the broken line c in FIG. 7, the AND circuit output 27 becomes the "1" level, and the
The MOS transistor 22 becomes conductive, and the output 26 becomes the ground potential only while the AND circuit output 27 is at the "1" level. Furthermore, the phase of pulse 14 is
If this matches the pulse 15, the OR circuit output 25 remains at the "1" level, the AND circuit output 27 remains at the "0" level, and the output 26 becomes open.

Therefore, by inputting the output 26 of the phase detection circuit shown in FIG. 6 to the known low-pass filter 17, a voltage obtained by integrating the output 26 can be obtained. That is, pulse 14 has phase c
If the pulse 14 is in phase b, the DC voltage gradually increases, and if the pulse 14 is in phase b, the DC voltage gradually decreases toward the ground potential. The voltage may be 18.

FIG. 8 shows an embodiment of the oscillator 5 of FIG. 4.
The oscillator in FIG. 8 is basically the same as that in FIG. The difference is that in place of the capacitor 10 in FIG. 3, a known variable capacitance diode 28 whose capacitance value can be varied by an applied reverse DC voltage is used. Note that the capacitor 29 is of a direct current type or a disconnect type type, and usually has a capacitance value sufficiently larger than that of the diode 28. Therefore, the oscillation frequency of the oscillator shown in FIG. 8 can be varied by changing the capacitance value of the diode 28. In other words, with the configuration shown in FIG. 8, a voltage controlled oscillator whose oscillation frequency can be varied by the DC voltage applied to the input terminal 30 can be realized. Furthermore, the capacitance value of the diode 28 decreases as the applied reverse voltage increases, so as the applied DC voltage of the input terminal 30 increases, the oscillation frequency of the oscillator increases, and as the applied DC voltage decreases, the oscillation frequency decreases. Here, if the frequency control voltage 18 obtained as explained in FIGS. 6 and 7 is inputted to the input terminal 30 of the oscillator in FIG.
In the figure, the frequency of the oscillator 5 is controlled so that the phase of the pulse 14 always matches the phase of a.

Note that the waveforms of the pulses 14 and 15 are not limited to the waveforms shown in FIG. 5 or 7; for example, the pulse 14' shown in FIG. 9 may be used.
The pulse 14' has a phase such that it changes from the "0" level to the "1" level at the m-th pulse phase of the output 6 of the oscillator 5. Such pulses can also be easily obtained using a known circuit including the frequency divider 12 and decoder 13 shown in FIG. When using the pulse 14', the phase detection circuit 16 shown in the embodiment shown in FIG. 10 may be used. FIG. 10 shows a configuration in which a known T-type flip-flop (hereinafter abbreviated as TFF) 31 is added to the circuit of FIG. 6. In addition, the first
In FIG. 0, MOS transistors 21 and 22 are connected in the same way as in FIG. 6, but illustration is omitted. Pulses 14', 2 are applied to input terminal 23 in FIG.
4, pulse 14' to the clock input terminal T of TFF31, and pulse 15 to the reset terminal R of the TFF31.
2, the phase in which the pulse 14' changes from the "0" level to the "1" level is the phase in which the pulse 14' changes from the "1" level to the "0" level, and the phase in which the pulse 15 changes from the "0" level to the "1" level. A pulse 32 that changes from the "0" level to the "1" level is obtained. 10 in place of the two-input OR circuit 19 in FIG.
If the 3-input OR circuit 33 shown in the figure is used and the pulse 32 is input as shown, the same outputs as those explained in FIG. 7 can be obtained at the OR circuit output 25 and the AND circuit output 27.

Furthermore, the pulse 15 is not limited to the illustrated example described above. In short, from the time when the oscillator 5 in FIG. 4 restarts oscillation after a temporary stop, the oscillator 5 operates with a pulse having the pulse phase of the n-th oscillation output 6 and a repetition frequency f _H obtained from the output of the oscillator 1. The present invention can be realized by using a pulse having a phase different from that of the stop period (t _S in FIG. 5), and there are no restrictions on the pulse width or polarity of each pulse.

Another embodiment of the present invention will be described with reference to FIGS. 11 to 14. FIG. 11 is a configuration diagram thereof, and FIG. 12 is a signal waveform diagram in FIG. 11. The difference between the embodiment shown in FIG. 11 and the embodiment shown in FIG. 4 is that in FIG. be. Pulse 15 is applied to the pulse width adjustment circuit 34.
is input, and at its output, as shown in _FIG . If you get 35, you get the first
With the configuration shown in FIG. 1, the same effect as the embodiment shown in FIG. 4 can be obtained.

FIG. 13 shows an embodiment of the pulse width adjustment circuit 34 shown in FIG. 11. The TFF 36, inverter circuits 37 and 38, a resistor 39, and a capacitor 40 are connected as shown, and a pulse 15 is input to an input terminal 41. At this time, as shown in the operating waveform diagram of FIG. 14, the input 42 of the inverter circuit 38 has a waveform in which the transient part of the pulse 15 is blunted due to the resistor 39 and the capacitor 40, and the output pulse 43 is the input pulse Pulse 1 depending on the degree of transient part rounding of 42
It has a phase that lags behind that of 5. pulse 43
Input to reset terminal R of TFF36, pulse 1
5 is input to the clock input terminal T via the inverter circuit 37, as shown in FIG.
When the pulse 15 changes from the "1" level to the "0" level, it changes from the "1" level to the "0" level, and a pulse 35 having a pulse width t _S corresponding to the time constant determined by the resistor 39 and the capacitor 40 is obtained. It will be done.
Note that the above pulse width adjustment circuit can also be easily realized using a monostable multivibrator, which is a known digital circuit.

By the way, in equation (1), the determined n and
It can be seen that the oscillation frequency f ₀ of the oscillator 5 changes if t is changed with respect to the value of T ₁ . As is clear from FIG. 5, t can be changed by changing _tS . Therefore, in FIG. 11, by changing _tS in the pulse width adjustment circuit 34, n and
The setting of the oscillation frequency of the oscillator 5 can be varied by setting T ₁ to a constant value. The pulse width t _S can be varied, for example, by
This can be easily realized by using a variable resistor as the resistor 39 shown in FIG. By varying the above t _S to set the oscillation frequency of the oscillator 5, the initial variation t in FIG _. It also becomes possible to adjust and absorb the oscillation frequency of the oscillator 5 and precisely set the oscillation frequency of the oscillator 5.

As explained above, according to the present invention, the oscillator for generating horizontal clock pulses temporarily stops for each horizontal period of the television signal, and from the time when the oscillator starts oscillating again, the phase of the predetermined number of pulses of the oscillator output is as follows: Since the oscillation frequency of the oscillator is always controlled to have the repetition period of the horizontal period of the television signal, the oscillation frequency of the oscillator can be stabilized against fluctuations in the operating power supply voltage or temperature. By making it variable,
The oscillation frequency setting can be made variable.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional example, FIG. 2 is a signal waveform diagram of each part thereof, and FIG. 3 is a configuration diagram of the oscillator 5 in FIG. 1.
4 is a configuration diagram of an embodiment of the present invention, FIG. 5 is a signal waveform diagram of each part thereof, FIG. 6 is a diagram of an embodiment of the phase detection circuit of FIG. 4, and FIG. 7 is a signal waveform diagram of each part thereof,
FIG. 8 is a block diagram of an embodiment of the oscillator 5 shown in FIG.
The figure is a waveform diagram showing another example of the signals of each part in Figure 4.
0 is a block diagram showing another embodiment of the phase detection circuit of FIG. 4, FIG. 11 is a block diagram of another embodiment of the present invention,
Fig. 12 is a signal waveform diagram of each part, Fig. 13 is a diagram of the first signal.
Example configuration diagram of the pulse width adjustment circuit in FIG. 1, No. 14
The figure is a diagram of signal waveforms at each part. Explanation of symbols 1, 5...Oscillator, 2, 12...
Frequency divider, 3, 13... decoder, 16... phase detection circuit, 17... low pass filter, 34... pulse width adjustment circuit.

Claims (1)

[Claims] 1. A first oscillation means, and the output of this first oscillation means is frequency-divided so that the repetition frequency is the same and the first and second oscillation means are
and a third means for generating pulses having different phases, and a voltage control type in which the oscillation operation stops during the period from the first phase to the second phase and the oscillation frequency is controlled by an input control voltage. and a second oscillation means that divides the oscillation output from the time when the second oscillation means stops oscillation for the above-mentioned period and starts oscillation again, and generates a second oscillation means corresponding to the predetermined number of output pulse phases. means for generating a pulse having a phase of 4, phase detecting the third pulse phase and the fourth pulse phase, and outputting the detected output through a low-pass filter circuit to an input control voltage of the second oscillating means; 1. An oscillation device comprising: a phase detection means, wherein the output of the second oscillation means is used as a device output. 2. In the device according to claim 1,
An oscillation device characterized in that the second oscillation means is an oscillation means that can variably set the oscillation stop period.